Lattice Semiconductor MachXO5-NX Development Kit, User Manual

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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FPGA-EB-02052-0.90 29
MIPI Camera Sensor Input Header
(J8) Pin Number
Net Name MachXO5-25 Ball Location
3 DPHY0_CKP T14
4 GND —
5 DPHY0_DN3 N12
6 DPHY0_DP3 N13
7 GND —
8 DPHY0_DN1 R13
9 DPHY0_DP1 P13
10 GND —
11 DPHY0_DN0 T13
12 DPHY0_DP0 U13
13 GND —
14 DPHY0_DN2 U14
15 DPHY0_DP2 V13
16 GND —
17 GND —
18 VDD2V8 —
19 NC —
20 DPHY0_CLK K7
21 DPHY0_FSYNC K6
22 DPHY0_SDA H5
23 DPHY0_SCL H6
24 DPHY0_RST H7
25 CVDD —
26 VRAM (DVDD1V8)
27 GND —
28 GND —
29 AVDD2V8 —
30 GND —
Figure 8.2. MIPI Camera Sensor Power Supply Header
8.8. User I
2
C Interface
This board provides more options for user I
2
C access from different MachXO5-25 Wide Range I/O to multiple onboard
headers. They are solid connected for target applications, but those connections to bridge SDA0/SCL0 are not
populated in default. You need to build your interconnection for I
2
C applications across the board. For example, if you
want to use an Ardvark I
2
C host to access FX12 adapt board, you can use internal fabric logic of MachXO5-25 to bridge