Lattice Semiconductor MachXO5-NX Development Kit, User Manual

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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FPGA-EB-02052-0.90 13
output tri-state mode, avoiding multi-drivers on those shared signals. The JTAG connections between J1 and
MachXO5-25 are listed in
Table 3.1 .
Figure 3.3. Level Shift for JTAG Download Interface
Figure 3.4. JTAG Test Header
Table 3.1. Config JTAG Connections
J1 Pin Number JTAG Net Name
MachXO5-25 Ball Location
for JTAG
Optional SSPI Function
1 VCCIO2 — —
2 NX_TDO E20 SSI
3 NX_TDI E18 SSO
4 — — —
5 — — —
6 NX_TMS F16 SCSN
7 GND — —
8 NX_TCK G16 SCLK