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FPGA-EB-02028-1.4
27
CN1 Pin Name
Signal Name
LIFCL-40 Ball
21
NO Connect
—
22
CAM_SDA
W5
23
CAM_SCL
Y5
24
CAM_RESET
W18
25
V1P2
—
26
V1P8
—
27
GND
—
28
GND
—
29
V2P8
—
30
GND
—
8.5.
D-PHY1 Header
Table 8.5. D-PHY1 J6 Header Pin Connections
J6 Pin Name
Signal Name
LIFCL-40 Ball
1
GND
—
2
GND
—
3
DPHY1_CKP
A8
4
DPHY1_CKN
B8
5
GND
—
6
GND
—
7
DPHY1_DP0
A7
8
DPHY1_DN0
B7
9
GND
—
10
GND
—
11
DPHY1_DP1
A9
12
DPHY1_DN1
B9
13
GND
—
14
GND
—
15
DPHY1_DP2
A6
16
DPHY1_DN2
B6
17
GND
—
18
GND
—
19
DPHY1_DP3
A10
20
DPHY1_DN3
B10