Lattice Semiconductor LIFCL-40-EVN, User Manual

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CrossLink-NX Evaluation Board
User Guide
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FPGA-EB-02028-1.4 15
4. Programming and I
2
C
The JTAG/SPI programming architecture and I
2
C interface of the CrossLink-NX Evaluation Board is shown in Figure 4.1 .
Mini USB
(J2)
FT2232H
(U1)
rst#
UART (DNI
2
)
I2C
JTAG
LIFCL
(U3)
JTAG Header (J1)
DNI
1
Raspberry Pi (JP5)
Raspberry Pi (JP5)
D
N
I 3
SPI
Flash
(U6)
SPI Header
(J20)
Port 0
Port 1
JP1
Notes:
1. Via DNI 0 resistors R35, R36, R37 and R38
2. Via DNI 0 resistors R15 and R17
3. Via DNI 0 resistors R39 and R40
Figure 4.1. Configuration and I
2
C Architecture
4.1. JTAG Download Interface
The CrossLink-NX Evaluation Board has a built-in download controller for programming the CrossLink-NX device. It uses
an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download
cable, connect the USB cable from a PC with Radiant Programmer tool installed to the mini USB connector on the board
(J2). A mini USB to USB-A cable is included in the CrossLink-NX Evaluation Kit. The USB hub on the PC detects the cable
of the USB function on Port 0, making the built-in cable available for use with the Radiant programming software.
4.2. Alternate JTAG Download Interface
J1 is an 8-pin standalone JTAG header used with an external Lattice download cable that is available separately, when
the FTDI part is disabled from the JTAG chain after setting the JP1 jumper. A USB download cable can be attached to
the board using J1 to interface with the CrossLink-NX. For details on the connection between the USB download cable
and J1, refer to
Programming Cable User’s Guide (FPGA-UG-02042) .
J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path
through the Raspberry Pi header (JP5) for customer applications. This is done by connecting the JP5 header to the J1
header through some onboard resistors. The JTAG connections between J1 and JP5 are listed in
Table .
Table 4.1. JTAG Connections
J1 Pin
Number
JTAG Signal
Name
CrossLink-NX Ball
Location for JTAG
Raspberry Pi Header
(JP8) Pin Number
J1 to JP5 Isolation
(Assembly)
Raspberry Pi GPIO
1 VCCIO1 — — — —
2 TDO F19 10 R36 (DNI) IO15
3 TDI F17 11 R38 (DNI) IO17
4 — — — — —
5 — — — — —
6 TMS F15 12 R37 (DNI) IO18
7 GND — — — —
8 TCK G18 8 R35 (DNI) IO14