of the PWM output.
If a duty cycle of 0.0% (totally off) is required, consider using a simple inverter IC such as the CD74ACT540E from TI. Or you can
switch the mode of the timer to some input mode, and add an external pull-down to hold the line low when set to input.
2.9.1.2 - PWM Output (8-Bit, Mode 1)
Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the
total time is spent low (out of 65536 total increments). The lower byte is actually ignored since this is 8-bit PWM. That means the
duty cycle can be varied from 100% (0 out of 65536 are low) to 0.4% (65280 out of 65536 are low).
The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2
8
.
The following table shows the range of available PWM frequencies based on timer clock settings.
PWM8 Frequency Ranges
TimerClockBase
Divisor=1
Divisor=256
0
4 MHz
15625
N/A
1
12 MHz
46875
N/A
2
48 MHz (default)
187500
N/A
3
1 MHz /Divisor
3906.25
15.259
4
4 MHz /Divisor
15625
61.035
5
12 MHz /Divisor
46875
183.105
6
48 MHz /Divisor
187500
732.422
Table 2.9.1.2-1. 8-bit PWM Frequencies
Note that the clocks above apply to the U3 hardware revision 1.21. With hardware revision 1.20 all clocks are half of those values.
The same clock applies to all timers, so all 8-bit PWM channels will have the same frequency and will have their falling edges at
the same time.
PWM output starts by setting the digital line to output-low for the specified amount of time. The output does not necessarily start
instantly, but rather waits for the internal clock to roll. For example, if the PWM frequency is 100 Hz, that means the period is 10
milliseconds, and thus after the command is received by the device it could be anywhere from 0 to 10 milliseconds before the start
of the PWM output.
If a duty cycle of 0.0% (totally off) is required, consider using a simple inverter IC such as the CD74ACT540E from TI. Or you can
switch the mode of the timer to some input mode, and add an external pull-down to hold the line low when set to input.
2.9.1.3 - Period Measurement (32-Bit, Modes 2 & 3)
Mode 2: On every rising edge seen by the external pin, this mode records the number of clock cycles (clock frequency determined
by TimerClockBase/TimerClockDivisor) between this rising edge and the previous rising edge. The value is updated on every
rising edge, so a read returns the time between the most recent pair of rising edges.
In this 32-bit mode, the processor must jump to an interrupt service routine to record the time, so small errors can occur if another
interrupt is already in progress. The possible error sources are:
Other edge interrupt timer modes (2/3/4/5/8/9/12/13). If an interrupt is already being handled due to an edge on the other
timer, delays of a few microseconds are possible.
If a stream is in progress, every sample is acquired in a high-priority interrupt. These interrupts could cause delays on the
order of 10 microseconds.
The always active U3 system timer causes an interrupt 61 times per second. If this interrupt happens to be in progress when
the edge occurs, a delay of about 1 microsecond is possible. If the software watchdog is enabled, the system timer interrupt
takes longer to execute and a delay of a few microseconds is possible.
Note that the minimum measurable period is limited by the edge rate limit discussed in Section 2.9.2.
See Section 3.2.1 for a special condition if stream mode is used to acquire timer data in this mode.
Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is
detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.
Mode 3 is the same except that falling edges are used instead of rising edges.
2.9.1.4 - Duty Cycle Measurement (Mode 4)
Records the high and low time of a signal on the external pin, which provides the duty cycle, pulse width, and period of the signal.
Returns 4 bytes, where the first two bytes (least significant word or LSW) are a 16-bit value representing the number of clock ticks
during the high signal, and the second two bytes (most significant word or MSW) are a 16-bit value representing the number of
clock ticks during the low signal. The clock frequency is determined by TimerClockBase/TimerClockDivisor.
The appropriate value is updated on every edge, so a read returns the most recent high/low times. Note that a duty cycle of 0% or
100% does not have any edges.
To select a clock frequency, consider the longest expected high or low time, and set the clock frequency such that the 16-bit
registers will not overflow.
Note that the minimum measurable high/low time is limited by the edge rate limit discussed in Section 2.9.2.
When using the LabJackUD driver the value returned is the entire 32-bit value. To determine the high and low time this value
should be split into a high and low word. One way to do this is to do a modulus divide by 2
16
to determine the LSW, and a normal
divide by 2
16
(keep the quotient and discard the remainder) to determine the MSW.
Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is
detected. If a timer is reset and read in the same function call, the read returns the value just before the reset. The duty cycle reset
is special, in that if the signal is low at the time of reset, the high-time/low-time registers are set to 0/65535, but if the signal is high
at the time of reset, the high-time/low-time registers are set to 65535/0. Thus if no edges occur before the next read, it is possible
to tell if the duty cycle is 0% or 100%.
2.9.1.5 - Firmware Counter Input (Mode 5)
On every rising edge seen by the external pin, this mode increments a 32-bit register. Unlike the pure hardware counters, these
timer counters require that the firmware jump to an interrupt service routine on each edge.
Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will return zero until a new edge is
detected. If a timer is reset and read in the same function call, the read returns the value just before the reset.
2.9.1.6 - Firmware Counter Input With Debounce (Mode 6)
17
