1 Timer enabled, Counter0 disabled, Counter1 enabled, and TimerCounterPinOffset=6:
FIO6=Timer0
FIO7=Counter1
2 Timers enabled, Counter0 enabled, Counter1 enabled, and TimerCounterPinOffset=8:
EIO0=Timer0
EIO1=Timer1
EIO2=Counter0
EIO3=Counter1
Starting with hardware revision 1.30, timers/counters cannot appear on FIO0-3, and thus
TimerCounterPinOffset must be 4-8
.
A value of 0-3 will result in an error. This error can be suppressed by a power-up default setting in LJControlPanel. If suppressed, a
0-3 will result in an offset of 4.
Timers and counters can appear on various pins, but other I/O lines never move. For example, Timer1 can appear anywhere from
FIO4 to EIO1, depending on TimerCounterPinOffset and whether Timer0 is enabled. On the other hand, FIO5 (for example), is
always on the screw terminal labeled FIO5, and AIN5 (if enabled) is always on that same screw terminal.
Note that Counter0 is not available with certain timer clock base frequencies. In such a case, it does not use an external FIO/EIO
pin. An error will result if an attempt is made to enable Counter0 when one of these frequencies is configured. Similarly, an error
will result if an attempt is made to configure one of these frequencies when Counter0 is enabled.
Applicable digital I/O are automatically configured as input or output as needed when timers and counters are enabled, and stay
that way when the timers/counters are disabled.
See Section 2.8.1 for information about signal connections.
Each counter (Counter0 or Counter1) consists of a 32-bit register that accumulates the number of falling edges detected on the
external pin. If a counter is reset and read in the same function call, the read returns the value just before the reset.
The timers (Timer0-Timer1) have various modes available:
Index (Low-level & UD)
0
16-bit PWM output
1
8-bit PWM output
2
Period input (32-bit, rising edges)
3
Period input (32-bit, falling edges)
4
Duty cycle input
5
Firmware counter input
6
Firmware counter input (with debounce)
7
Frequency output
8
Quadrature input
9
Timer stop input (odd timers only)
10
System timer low read (default mode)
11
System timer hight read
12
Period input (16-bit, rising edges)
13
Period input (16-bit, falling edges)
Table 2.9-1. U3 Timer Modes
Both timers use the same timer clock.
There are 7 choices for the timer clock base:
Index (Low-level/UD)
0/20
4 MHz
1/21
12 MHz
2/22
48 MHz (default)
3/23
1 MHz /Divisor
4/24
4 MHz /Divisor
5/25
12 MHz /Divisor
6/26
48 MHz /Divisor
Table 2.9-2. U3 Timer Clock Base Options
Note that these clocks apply to the U3 hardware revision 1.21+. With hardware revision 1.20 all clocks are half of the values
above.
The first 3 clocks have a fixed frequency, and are not affected by TimerClockDivisor. The frequency of the last 4 clocks can be
further adjusted by TimerClockDivisor, but when using these clocks Counter0 is not available. When Counter0 is not available, it
does not use an external FIO/EIO pin. The divisor has a range of 0-255, where 0 corresponds to a division of 256.
Note that the DACs (Section 2.7) are derived from PWM signals that are affected by the timer clock frequency. The default timer
clock frequency of the U3 is set to 48 MHz, as this results in the minimum DAC output noise. If the frequency is lowered, the DACs
will have more noise, where the frequency of the noise is the timer clock frequency divided by 2
16
.
2.9.1 - Timer Mode Descriptions
2.9.1.1 - PWM Output (16-Bit, Mode 0)
Outputs a pulse width modulated rectangular wave output. Value passed should be 0-65535, and determines what portion of the
total time is spent low (out of 65536 total increments). That means the duty cycle can be varied from 100% (0 out of 65536 are low)
to 0.0015% (65535 out of 65536 are low).
The overall frequency of the PWM output is the clock frequency specified by TimerClockBase/TimerClockDivisor divided by 2
16
.
The following table shows the range of available PWM frequencies based on timer clock settings.
PWM16 Frequency Ranges
TimerClockBase
Divisor=1
Divisor=256
0
4 MHz
61.04
N/A
1
12 MHz
183.11
N/A
2
48 MHz (default)
732.42
N/A
3
1 MHz /Divisor
15.26
0.06
4
4 MHz /Divisor
61.04
0.238
5
12 MHz /Divisor
183.11
0.715
6
48 MHz /Divisor
732.42
2.861
Table 2.9.1.1-1. 16-bit PWM Frequencies
Note that the clocks above apply to the U3 hardware revision 1.21. With hardware revision 1.20 all clocks are half of those values.
The same clock applies to all timers, so all 16-bit PWM channels will have the same frequency and will have their falling edges at
the same time.
PWM output starts by setting the digital line to output-low for the specified amount of time. The output does not necessarily start
instantly, but rather waits for the internal clock to roll. For example, if the PWM frequency is 100 Hz, that means the period is 10
milliseconds, and thus after the command is received by the device it could be anywhere from 0 to 10 milliseconds before the start
of the PWM output.
16
