Kurzweil CUP2, Service Manual

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Size Document Number Rev
Date: Sheet of
Reproduction without the express written consent of Young Chang Co., Ltd. is prohibited.
By
Title
021402 DV2-A
RP2A ENGINE BOARD - SP4x Configuration
Young Chang R&D Institute
1432 Main St.
Waltham MA 02451
Friday, January 07, 2011
USA Copyright 2010 Young Chang Co., Ltd.
R. Folk
MARA
2 5
MARA 1 DECOUPLING CAPS
M1_ROM_D_1 is Don't Care on Power Up
VCC25 VCC33 VCC18
VCC18
VCC18 VCC33 VCC25 VCC18
VCC18 VCC33
VCC33
VCC18
VCC25
VCC33
VCC33
CPU_D_31
CPU_D_30
CPU_D_29
CPU_D_28
CPU_D_27
CPU_D_26
CPU_D_25
CPU_D_24
CPU_D_23
CPU_D_22
CPU_D_21
CPU_D_20
CPU_D_19
CPU_D_18
CPU_D_17
CPU_D_16
CPU_D_15
CPU_D_14
CPU_D_13
CPU_D_12
CPU_D_11
CPU_D_10
CPU_D_9
CPU_D_8
CPU_D_7
CPU_D_6
CPU_D_5
CPU_D_4
CPU_D_3
CPU_D_2
CPU_D_0
CPU_D_1
CPU_A_16
CPU_A_15
CPU_A_14
CPU_A_13
CPU_A_12
CPU_A_11
CPU_A_10
CPU_A_9
M1_SD_OUT_0
CPU_A_8
CPU_A_7
CPU_A_6
CPU_A_5
CPU_A_4
CPU_A_3
CPU_A_2
CPU_A_1
CPU_A_0
MARA1_VDDAN
M1_SD_IN_0
ROM_D_13
ROM_D_15
ROM_D_14
ROM_D_12
DDR_D_7
DDR_D_4
ROM_D_1
ROM_A_13
ROM_A_15
ROM_A_14
ROM_A_12
ROM_A_1
ROM_A_3
ROM_A_2
ROM_A_5
ROM_A_7
ROM_A_6
ROM_A_4
ROM_A_0
ROM_A_9
ROM_A_11
ROM_A_10
ROM_A_8
ROM_D_3
ROM_D_2
ROM_A_17
ROM_A_19
ROM_A_18
ROM_A_21
ROM_A_23
ROM_A_22
ROM_A_20
ROM_A_16
ROM_A_25
ROM_A_26
ROM_A_24
DDR_A_3
DDR_A_2
DDR_A_0
DDR_A_1
DDR_A_11
DDR_A_10
DDR_A_8
DDR_A_9
ROM_D_5
ROM_D_7
ROM_D_6
ROM_D_4
DDR_D_3
DDR_D_2
DDR_D_0
DDR_D_1
DDR_A_12
DDR_A_7
DDR_A_6
DDR_A_5
DDR_A_4
DDR_D_5
ROM_D_0
ROM_D_9
ROM_D_11
ROM_D_10
ROM_D_8
DDR_D_15
DDR_D_12
DDR_D_11
DDR_D_10
DDR_D_8
DDR_D_9
DDR_D_13
DDR_D_14
DDR_D_6
DDR_BA_1
DDR_BA_0
ROM_D_3
ROM_D_2
ROM_D_4
ROM_D_0
MARA1_GTOP
M1_REFCLK_OUT
VCC18_ISO_M1
M1_SMCH_IN
M1_SD_OUT_1
M1_SD_OUT_2
M1_SD_OUT_3
M1_TRST_L
M1_SD_OUT_4
CPU_A_[22:0] sh.1,3,4,5
CPU_D_[31:0] sh.1,3,4,5
CPU_WAIT_L sh.1,3,5
MARA_CS_L sh.1,5
MARA_WR_L sh.3
M1_DREQ_L sh.1,5
M1_DACK_L sh.1,5
ROM_CS1_L sh.4
ROM_D_[15:0] sh.4
ROM_A_[26:0] sh.4
DDR_DQS_2 sh.3
DDR_CAS_L sh.3
DDR_BA_[1:0] sh.3
DDR_RAS_L sh.3
DDR_WE_L sh.3
DDR_VREF sh.3
DDR_A_[12:0] sh.3
DDR_CLK_H sh.3
DDR_CLK_L sh.3
DDR_CKE sh.3
DDR_D_[15:0] sh.3
DDR_DQS_0 sh.3
ROM_OE_L sh.4
ROM_CS0_L sh.4
DSP_RESET_L sh.3,5
M1_CLK12_288_IN sh.3
M1_I2S_BCLK sh.4
M1_I2S_LRCK sh.4
M1_SD_OUT_[3:0] sh.4
M1_SDOUT_4 sh.1
1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DNS DNS
+ + + + + + + + + +
+ +
DNS DNS
DNS DNS
standard audio
hi speed audio
pll
system
cpu address
cpu data
cpu control
dma
MARA
rom data
rom address
internal scan
ddr sdram control
ddr sdram address
jtag
ddr sdram data
rom control
standard audio
hi speed audio
pll
system
cpu address
cpu data
cpu control
dma
MARA
rom data
rom address
internal scan
ddr sdram control
ddr sdram address
jtag
ddr sdram data
rom control
DHI_15
M2
DHI_14
M1
DHI_13
L1
DHI_12
L2
DHI_11
K1
DHI_10
K2
DHI_9
J1
DHI_8
J2
DHI_7
H1
DHI_6
H2
DHI_5
G1
DHI_4
G2
DHI_3
F1
DHI_2
F2
DHI_1
E1
DHI_0
E2
DLO_15
Y2
DLO_14
Y1
DLO_13
W2
DLO_12
W1
DLO_11
V2
DLO_10
V1
DLO_9
U2
DLO_8
U1
DLO_7
T2
DLO_6
T1
DLO_5
R2
DLO_4
R1
DLO_3
P2
DLO_2
P1
DLO_1
N2
DLO_0
N1
A_0
AC2
A_1
AD1
A_2
AD2
A_3
AE1
A_4
AF1
A_5
AE2
A_6
AE11
A_7
AF11
A_8
AE12
A_9
AF12
A_10
AE13
A_11
AF13
A_12
AF14
A_13
AE14
A_14
AF15
A_15
AE15
A_16
AF16
ROM_A_0
J26
ROM_A_1
J25
ROM_A_2
H26
ROM_A_3
H25
ROM_A_4
G26
ROM_A_5
G25
ROM_A_6
F26
ROM_A_7
F25
ROM_A_8
E26
ROM_A_9
E25
ROM_A_10
D26
ROM_A_11
D25
ROM_A_12
C26
ROM_A_13
C25
ROM_A_14
B26
ROM_A_15
A26
ROM_A_16
B25
ROM_A_17
A25
ROM_A_18
B24
ROM_A_19
A24
ROM_A_20
B23
ROM_A_21
A23
ROM_A_22
B22
ROM_A_23
A22
ROM_A_24
B21
ROM_A_25
A21
ROM_A_26
B20
CFG_0/ROM_D_0
W25
CFG_1/ROM_D_1
W26
CFG_2/ROM_D_2
V25
CFG_3/ROM_D_3
V26
CFG_4/ROM_D_4
U25
ROM_D_5
U26
ROM_D_6
T25
ROM_D_7
T26
ROM_D_8
R25
ROM_D_9
R26
ROM_D_10
P26
ROM_D_11
P25
ROM_D_12
N26
ROM_D_13
N25
ROM_D_14
M26
ROM_D_15
M25
DDR_A_0
A18
DDR_A_1
B17
DDR_A_2
A17
DDR_A_3
B16
DDR_A_4
A16
DDR_A_5
B15
DDR_A_6
A15
DDR_A_7
B14
DDR_A_8
A14
DDR_A_9
A13
DDR_A_10
B13
DDR_A_11
A12
DDR_A_12
B12
DDR_D_0
A9
DDR_D_1
B9
DDR_D_2
A8
DDR_D_3
B8
DDR_D_4
A7
DDR_D_5
B7
DDR_D_6
A6
DDR_D_7
B6
DDR_D_8
A3
DDR_D_9
A2
DDR_D_10
B3
DDR_D_11
A1
DDR_D_12
B2
DDR_D_13
B1
DDR_D_14
C2
DDR_D_15
C1
VCC33
AA3
VCC33
AA4
VCC33
AB3
VCC33
AB4
VCC33
AC3
VCC33
AC9
VCC33
AC10
VCC33
AC14
VCC33
AC15
VCC33
AC16
VCC33
AC20
VCC33
AC21
VCC33
AC22
VCC33
AC23
VCC33
AC24
VCC33
AD9
VCC33
AD10
VCC33
AD14
VCC33
AD15
VCC33
AD16
VCC25
C4
VCC25
C5
VCC25
C11
VCC25
C13
VCC25
C15
VCC25
C19
VCC25
D5
VCC25
D11
VCC25
D13
VCC25
D15
VCC25
D19
VCC25
C9
VCC25
C14
VCC25
C16
VCC25
D9
VCC25
D14
VCC25
D16
GND
AC11
GND
AC13
GND
AC17
GND
AD3
GND
C3
GND
D4
GND
L11
GND
M12
GND
M13
GND
M14
GND
M15
GND
N12
GND
N13
GND
N14
GND
N15
GND
N23
GND
N24
GND
P12
GND
P13
GND
P14
GND
P15
GND
R12
GND
R13
GND
R14
GND
R15
GND
W23
GND
W24
GND
D1
GND
C6
GND
C7
GND
C8
GND
C20
GND
D6
GND
D7
GND
D8
GND
D20
GND
L12
GND
L13
GND
L14
GND
L15
GND
C10
VCC18
C12
VCC18
C18
VCC18
D12
VCC18
D18
GND
C17
GND
D10
GND
D17
TDO
AE7
TDI
AF9
TCK
AF7
TMS
AE3
TRST_L
AF8
CE_L
AA1
DACK_L
AA2
DREQ_L
AB1
READY/DTACK_L
AB2
WR_L
AC1
VDDAN
AE4
VSSAN
AF3
PLL_BYPASS
AF4
PLL_TST_1
AE5
PLL_TST_0
AF5
TEST_MODE
AE6
SCANENABLE
AF2
SD_OUT_0
AE16
SD_OUT_1
AF17
SD_OUT_2
AE17
SD_OUT_3
AF18
SD_OUT_4
AE18
SD_OUT_5
AF19
SD_OUT_6
AE19
SD_OUT_7
AF20
SD_IN_0
AE23
SD_IN_1
AF24
SD_IN_2
AF25
SD_IN_3
AE24
SD_IN_4
AF26
SD_IN_5
AE25
SD_IN_6
AE26
SD_IN_7
AD25
I8S_SCLK
AE20
I8S_SYNC
AF21
I2S_SCLK
AE21
I2S_SYNC
AF22
LJ_SCLK
AE22
LJ_SYNC
AF23
SMOOCH_OUT_0
AC25
SMOOCH_OUT_1
AC26
SMOOCH_OUT_2
AB25
SMOOCH_OUT_3
AB26
SMOOCH_IN_0
AA25
SMOOCH_IN_1
AA26
SMOOCH_IN_2
Y25
SMOOCH_IN_3
Y26
GTOP
AF10
RESET_L
AF6
CLK
AE9
ROM_CS_0/QSA_EVN_L
L26
ROM_WE_EVN_L
L25
ROM_CS_1/WE_ODD_L
K26
ROM_OE_L
K25
DDR_RAS_L
A20
DDR_WE_L
B19
DDR_CLK_H
A19
DDR_CLK_L
B18
DDR_BA_1
B11
DDR_BA_0
A11
DDR_CAS_L
A10
DDR_CKE
B10
DDR_DQS_0
A5
DDR_DQS_1
B5
DDR_DQS_2
A4
DDR_DQS_3
B4
VREF
D2
TST_CLK_OUT
AE10
VCC18
V3
VCC18
V4
VCC18
Y23
VCC18
Y24
VCC18
M3
VCC18
M4
REFCLK_OUT
AE8
GND
AC8
GND
AC4
GND
AB24
GND
AB23
GND
AC19
VCC18
L24
VCC18
L23
VCC18
K24
VCC18
K23
VCC18
H4
VCC18
H3
VCC18
AD7
VCC18
AD12
VCC18
AD18
VCC18
C21
VCC18
C22
VCC18
D21
VCC18
AC7
VCC18
AC12
VCC18
AC18
VCC18
AD4
VCC18
AD5
VCC18
AD6
VCC18
AA23
VCC18
AA24
VCC18
AC5
VCC18
AC6
VCC33
AD20
VCC33
AD21
VCC33
AD22
VCC33
AD23
VCC33
AD24
VCC33
AD26
VCC33
C24
VCC33
D3
VCC33
D23
VCC33
D24
VCC33
E3
VCC33
E4
VCC33
E23
VCC33
E24
VCC33
F3
VCC33
F4
VCC33
F23
VCC33
F24
VCC33
G23
VCC33
G24
VCC33
H23
VCC33
H24
VCC33
K3
VCC33
K4
VCC33
M23
VCC33
M24
VCC33
P3
VCC33
P4
VCC33
P23
VCC33
P24
VCC33
R3
VCC33
R4
VCC33
T3
VCC33
T4
VCC33
T23
VCC33
T24
VCC33
U23
VCC33
U24
VCC33
V23
VCC33
V24
VCC33
Y3
VCC33
Y4
GND
AD8
GND
AD11
GND
AD13
GND
AD17
GND
AD19
GND
C23
GND
D22
GND
G3
GND
G4
GND
J3
GND
J4
GND
J23
GND
J24
GND
L3
GND
L4
GND
L16
GND
M11
GND
M16
GND
N3
GND
N4
GND
N11
GND
N16
GND
P11
GND
P16
GND
R11
GND
R16
GND
R23
GND
R24
GND
T11
GND
T12
GND
T13
GND
T14
GND
T15
GND
T16
GND
U3
GND
U4
GND
W3
GND
W4
C55
0.1uF
C55
0.1uF
TP1
HEADER_POST
TP1
HEADER_POST
C76
100uF
C76
100uF
C71
0.1uF
C71
0.1uF
C89
0.1uF
C89
0.1uF
C69
0.1uF
C69
0.1uF
R103
110
R103
110
C68
0.1uF
C68
0.1uF
C65
22uF
C65
22uF
R11
1.0K R11
1.0K
C74
0.1uF
C74
0.1uF
C58
0.1uF
C58
0.1uF
C99
0.1uF
C99
0.1uF
R102
220
R102
220
R23
10K
R23
10K
C52
0.1uF
C52
0.1uF
C85
0.1uF
C85
0.1uF
C53
0.1uF
C53
0.1uF
C95
0.1uF
C95
0.1uF
C61
0.1uF
C61
0.1uF
C90
1uf
0805
C90
1uf
0805
C93
0.1uF
C93
0.1uF
R22
10K
R22
10K
C57
0.1uF
C57
0.1uF
C80
0.1uF
C80
0.1uF
C83
0.1uF
C83
0.1uF
C91
1uf
0805
C91
1uf
0805
C75
0.1uF
C75
0.1uF
L7
600 OHM @ 100MHz
L7
600 OHM @ 100MHz
RN13
22
RN13
22
C82
0.1uF
C82
0.1uF
C92
100uF
C92
100uF
C84
0.1uF
C84
0.1uF
C97
10uf
C97
10uf
C96
0.1uF
C96
0.1uF
C59
0.1uF
C59
0.1uF
R33
10
R33
10
C72
0.1uF
C72
0.1uF
C79
0.1uF
C79
0.1uF
C64
100uF
C64
100uF
C66
22uF
C66
22uF
C63
0.1uF
C63
0.1uF
C87
0.1uF
C87
0.1uF
C100
22uF
C100
22uF
RN12
10K
RN12
10K
C73
0.1uF
C73
0.1uF
C94
0.1uF
C94
0.1uF
C70
0.1uF
C70
0.1uF
R34 22 R34 22
C78
0.1uF
C78
0.1uF
C67
0.1uF
C67
0.1uF
C56
0.1uF
C56
0.1uF
C62
0.1uF
C62
0.1uF
C86
0.1uF
C86
0.1uF
C88
0.1uF
C88
0.1uF
C81
10uf
C81
10uf
C54
0.1uF
C54
0.1uF
C98
10uf
C98
10uf
C101
0.1uF
C101
0.1uF
U5
MARA
U5
MARA
L6
600 OHM @ 100MHz
L6
600 OHM @ 100MHz C60
0.1uF
C60
0.1uF
R26
10K
R26
10K
CUP2 Service Manual
7- 4