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2-6
ePCI-101 User’s Guide
2.2.3
Memory Interface
This product supports up to 1GB on 1 x 184-pin latching DIMM sockets. Supported memory includes
PC-1600/PC-2100/PC-2400 DDR, and a non-ECC/ECC mode.
2.2.3.1
Memory Scrubbing
This feature allows the chipset to automatically correct ECC errors and write back good data into
memory without the CPU intervening. This is done in hardware.
2.3
Intel ICH4
2.3.1
Enhanced IDE Interfaces (J4 and J9)
The board features a two-channel Bus Master PCI EIDE that is dedicated to Primary IDE logical
interface. Each channel supports up to two devices (including CD-ROMs, hard disks, and
CompactFlash) with independent timings, using a Master/Slave combination.
Signal Paths:
Primary IDE interface: J4 (40-pin header) and J15 (CompactFlash connector) and Secondary IDE
interface: J9 (40-pin header).
Related Jumpers:
JP7: when jumper is present, the CompactFlash is in “master” mode; otherwise it is in “slave”
mode.
Pin
Signal
Pin
Signal
1 RST#
2 GND
3 D7
4 D8
5 D6
6 D9
7 D5
8 D10
9 D4
10 D11
11 D3
12 D12
13 D2
14 D13
15 D1
16 D14
17 D0
18 D15
19 GND
20 N.C. (KEY)
21 DMARQ
22 GND
23 IOW#
24 GND
25 IOR#
26 GND
27 IORDY
28 GND (CSEL)
29 DMACK#
30 GND
31 IRQ
32 N.C. (IOCS16#)
33 A1
34 N.C.
(PDIAG#)
35 A0
36 A2
37 CS0#
38 CS1#
39 ACT#
40 GND
Summary of Contents for ePCI-101
Page 24: ...2 1 ePCI 101 User s Guide 2 1 Block Diagram...
Page 83: ...D 1 ePCI 101 User s Guide D Board Diagrams D 1 Top Devices Surface Mount...
Page 84: ...D 2 ePCI 101 User s Guide D 2 Bottom Devices Surface Mount...
Page 85: ...D 3 ePCI 101 User s Guide D 3 Mounting Holes...
Page 86: ...D 4 ePCI 101 User s Guide D 4 Top Mounting Components...