Kontron AM4904, User Manual

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Operating the Unit
67 AM4904 User Guide
www.kontron.com
The standard usage of these clocks is (CLK1...3 as of mTCA spec, TCLKA...D as of AMC.0 R2.0 spec):
• CLK1 (output clock to AMC TCLKA/C)
• CLK2 (input clock from AMC TCLKB/D)
• CLK3 (output clock to AMC FCLK)
Nonetheless, the CLK1 and CLK2 signals to each AMC can be configured as input or output independently.
So, the MCH is prepared to route every incoming reference clock to any AMC TCLK and can use any incoming
backplane or BITS lock as reference clock, e.g. MCH CLK1 can be routed as output clock to AMC TCLKA and
MCH CLK2 can be routed to AMC TCLKB.
The DPLL also supports wander and jitter filtering by configurable filter settings (default filter bandwidth is
1.7 Hz, selectable range: 0.1- 7 Hz). There are additionaly several configurable DPLL parameters as Pull-In/
Hold-in range and Phase Slope Linits. For additional information on how to use these features, please con-
tact the Kontron support.
For information about CM clocking CLI commands, refer to chapter "Clock Commands" on page 58.
3.4.7.1 Example 1
This example describes how to configure the AM4904 to receive an external clock as primary input for the
onboard PLL.
For the example the default mode (Automatic Normal Mode) is chosen.
clicm clock config show
STATUS VALUE DESCRIPTION
========================== ======== ===============================================
PLL Mode 0x03 Automatic Normal Mode
PLL Holdover Mode 0x01 detected
PLL Lock Mode 0x00 not detected
Reference Select Fail 0x01 detected
PLL Pull-in range 0x03 +/- 83 ppm (Stratum 4, G.824)
Reference Switch Mask 0x0c GST, PFM,
Reference Holdover Mask 0x03 SCM, CFM,
Wait to Restore 0x00 0 min
Disqualify time 0x0a 2.5 s
Qualify time 0x01 4 * 2.5 s
Hitless Switching 0x00 enabled (build-out phase differents)
Bandwidth 0x01 1.7 Hz
Phase slope limits 0x03 unlimited
Holdover update time 0x00 26 ms
Holdover filter bandwidth 0x00 bypass, no filtering
Select PLL Reference
For using an external clock as reference input for the PLL the source has to be selected.
In this example the CLK input on the front is used with a 8kHz clock connected.
# clicm clock reference primary front