Kontron AM4904, User Manual

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Operating the Unit
66 AM4904 User Guide
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The PLL supports the following operation mode:
• Manual Normal Mode
In this mode, automatic reference switching is disabled and the selected reference is determined by the
mode selection parameter. If the selected reference fails, the device automatically enters the holdover
mode.
• Manual Holdover Mode
In this mode, automatic reference switching is disabled and DPLL1 stays in the holdover mode.
• Manual Freerun Mode
In this mode, automatic reference switching is disabled and DPLL1 stays in the free-run mode.
• Automatic Normal Mode (default mode)
In this mode, automatic reference switching is enabled so that DPLL1 automatically selects the highest
priority qualified reference (primary reference). If that reference fails, an automatic reference switcho-
ver to the next highest priority (secondary reference) and qualified reference is initiated. If there are
no suitable references for selection, DPLL1 will stay in free-run or enter the holdover state.
The following parameters of the PLL can be configured:
The PLL synchronizes to telecom reference input clocks 2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz or to
Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz).
The PLL output synthesizers (P0, P1) generate telecom clock frequencies from any multiple of 8 kHz up to
100 MHz. So, the MCH is for example able to setup two different frequencies 1MHz and 20 MHZ.
The MCH has three clocks CLK1, CLK2, CLK3.
Table 3-28: PLL Settings
Parameter Value Description
hitless-switching enable, disable Configure hitless reference switching
revertive-switching enable, disable Configure revertive switching option
switch-mask SCM|CFM|GST|PFM, None
Set mask for failure indicators (SCM,CFM, PFM and
GST) used for automatic reference switching
holdover-mask SCM|CFM|GST|PFM, None
Set mask for failure indicators (SCM, CFM, GST and
PFM) used for automatic holdover
pull-in-range 12, 52, 130, 83 Set DPLL pull-in range value in ppm
wait-restore 0..15
Set time a failed reference must be fault free before it
is considered as available for synchronization
disqualify-time
0, 0.5ms, 1ms, 5ms, 10ms,
50ms, 100ms, 500ms, 1s, 2s,
2.5s, 4s, 8s, 16s, 32s, 64s
Set guard soak_timer control bits to disqualify the
reference
qualify-time 2, 4, 16, 32
Set timer control bits to qualify the reference in times
the time to disqualify
bandwidth 0.1, 1.7, 3.5, 14, 28, 890, fast Set PLL loop bandwidth in Hz
phase-slope 885ns, 7.5us, 61us, unlimited Set available phase slope limits
holdover-update 26ms, 1s, 10s, 60s Set holdover update time
holdover-filter bypass, 18mHz, 0.6Hz, 10Hz Set DPLL holdover post filtering bandwidth selection