188 Keysight CXG, EXG, and MXG X-Series Signal Generators Programming Guide
Programming the Status Register System
Status Groups
Table 4-4
Data Questionable Condition Register Bits
Bit
Description
0-2
Unused
. These bits are always set to 0.
3
Power (summary)
. This is a summary bit taken from the QUEStionable:POWer register. A 1 in this bit
position indicates that one of the following may have happened: The ALC (Automatic Leveling Control) is unable
to maintain a leveled RF output power (i.e., ALC is UNLEVELED), the reverse power protection circuit has been
tripped. See the
“Data Questionable Power Status Group” on page 190
for more information.
4
Unused
. This bit is always set to 0.
5
Frequency (summary)
. This is a summary bit taken from the QUEStionable:FREQuency register. A 1 in this
bit position indicates that one of the following may have happened: synthesizer PLL unlocked, 10 MHz
reference VCO PLL unlocked, 1 GHz reference unlocked, sampler, YO loop unlocked or baseband 1 unlocked.
For more information, see the
“Data Questionable Frequency Status Group” on page 193
6, 7
Unused
. These bits are always set to 0.
8
a
Calibration (summary)
. This is a summary bit taken from the QUEStionable:CALibration register. A 1 in this
bit position indicates that one of the following may have happened: an error has occurred in the DCFM zero
calibration, or an error has occurred in the I/Q calibration. See the
“Data Questionable Calibration Status
for more information.
9
Self Test
. A 1 in this bit position indicates that a self-test has failed during power-up. Reset this bit by cycling
the signal generator’s line power. *CLS will not clear this bit.
10, 11
Unused
. These bits are always set to 0.
12
b
BERT (summary).
This is a summary bit taken from the QUEStionable:BERT register. A 1 in this bit position
indicates that one of the following occurred: no BCH/TCH synchronization, no data change, no clock input,
PRBS not synchronized, demod/DSP unlocked, or demod unleveled. See the
for more information.
13, 14
Unused
. These bits are always set to 0.
15
Always 0
.
a. The data reported by this bit depends on the installed options.
b. In models that do not support Bit Error Rate Testing (Option N5180UN7B), this bit is always set
to 0.
Query:
STATus:QUEStionable:CONDition?
Response:
The
decimal
sum of the bits set to 1
Example:
The decimal value 520 is returned. The decimal sum = 512 (bit 9) + 8 (bit 3).
Summary of Contents for X-Series
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