Kenwood NEXEDGE NX-900 Service Manual Download Page 20

Page: 20 / 115

NX-900

5. PLL Frequency Synthesizer

5-1. VCTCXO (X1)

VCTCXO (X1) generates a reference frequency of

19.2MHz for the PLL frequency synthesizer. This reference
frequency is applied to pin 9 of the PLL IC (IC3) through the
buffer amplifi er (Q11) and is connected to the IF circuit as
a 2nd local signal through the Tripler (Q203). The VCTCXO
oscillation frequency is determined by the DC voltage of the
VC terminal. The VC voltage is fi xed at 1.65V by R1 and R2,
and is supplied to the VC terminal.

5-2. VCO

There are two VCOs (VCO1 and VCO2)
VCO1 (Q5) generates a carrier for the TA (Talk Around)

transmitter.

VCO2 (Q6) generates the 1st local signal for the receiver

and a carrier for the transmitter.

The oscillation frequency of the VCO is half of the carrier

or 1st local signal.

The VCO oscillates from 403 to 435MHz at transmission,

and 396.475 to 405.975MHz at reception.

The VCO oscillation frequency is determined by one

system of operation switching terminal “/T_R” and two sys-
tems of voltage control terminals “CV” and “ASSIST”.

The operation switching terminal, “/T_R”, is controlled

by the control line (/T_R) output from the ASIC (IC510).

When the /T_R logic is low, VCO2 is activated, and when

the /T_R logic is high, VCO1 is activated.

The voltage control terminals, “CV” and “ASSIST”, are

controlled by the PLL IC (IC3) and ASIC (IC510) and the
output frequency changes continuously according to the
applied voltage. For the modulation input terminal, “VCO_
MOD”, the output frequency changes according to the ap-
plied voltage. This is used to modulate the VCO output.

5-3. PLL IC (IC3)

The PLL IC compares the differences in phases of the

VCO oscillation frequency and the VCTCXO reference fre-
quency, returns the difference to the VCO CV terminal and
realizes the “Phase Locked Loop” for the return control.

This allows the VCO oscillation frequency to accurately

match (lock) the desired frequency.

When the frequency is controlled by the PLL, the fre-

quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 3.0V.

The desired frequency is set for the PLL IC by the ASIC

(IC510) through the 3-line “SDO1”, “P_SCK1”, “/PCS_RF”
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the “PLD” signal line. If the VCO is not
the desired frequency (unlocked), the “PLD” logic is low.

“PLL_MOD” receives the modulation data from DSP

(IC717).

5-4. Local Switch (D101, D205)

The connection destination of the signal output from the

buffer amplifier (Q420) is changed with the diode switch
(D101) that is controlled by the transmission power supply,
80T, and the diode switch (D205) that is controlled by the
reception power supply, 50R. If the 80T logic is high, it is
connected to a send-side pre-drive (Q150). If the 80T logic is
low, it is connected to a local amplifi er (Q208).

CIRCUIT DESCRIPTION

Loop
Filter

BUFF

AMP

BPF

Ripple

Filter

VCO

80C

TCXO

PLL

IC3