JYTEK PCIe/PXIe-6302, User Manual

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Figure 20 Continuous Raw Data Acquisition
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25
Figure 21 Acquisition State .................................................................................. 25
Figure 22 A/D conversion and sampling
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26
Figure 23 Terminal Block State Check .................................................................. 29
Figure 24 Open Thermocouple Detection
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30
Figure 25 Rising and falling edges of digital signals ............................................. 31
Figure 26 Digital Trigger Paraments
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32
Figure 27 Digital Trigger Acquisition .................................................................... 33
Figure 28 Start Trigger mode
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34
Figure 29 AI Continuous Paraments
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35
Figure 30 Signel Channel Continuous Acquisition ................................................ 35
Figure 31 Reference Trigger mode
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36
Figure 32 Retrigger mode ..................................................................................... 37
Figure 33 Retrigger Paraments
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38
Figure 34 Retrigger In Reference Trigger Mode ................................................... 38
Figure 35 Retrigger Complete State
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38
Figure 36 SSI Connector in PCIe-6302 .................................................................. 39
Figure 37 DIP Switch in PCIe-6302
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40
Table 1 63xx on different buses
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5
Table 2 6302 channel grouping
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6
Table 3 Input Characteristics .................................................................................. 8
Table 4 Timing and Trigger Specification
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8
Table 5 Physical and Environment ......................................................................... 9
Table 6 Pinout defination
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10
Table 7 Voltage Accuracy ..................................................................................... 11
Table 8 Input noise
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12
Table 9 Input Stability .......................................................................................... 15
Table 10 Temperature Accuracy
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16
Table 11 Measurement sensitivity
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16
Table 12 Supported Linux Versions
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17
Table 13 A/D conversion time at different speed levels
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23
Table 14 ADC Timing Modes and maximum aggregate sampling rate ................ 27
Table 15 SSI Connector Pin Assignment for PCIe-6302
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39
Table 16 Relationship between switch position and slot number ....................... 40