PCIe/PXIe-6302 |
| 27
Table 14 ADC Timing Modes and maximum aggregate sampling rate
When the user sets the timing mode to Auto, the driver internally reverses the
current actual total sample rate according to the following formula:
����� ������ ���� = max number of channels on any one ADC ∗ ������ ����
Among them:
����� ������ ����
:
Current actual total sampling rate
max number of channels on any one ADC
:
Maximum number of channels
added on a single ADC
������ ����
:
User-set sampling rate
After the drive internally finds the actual total sampling rate, the lowest timing mode
is automatically selected according to the interval divided in above Table 14.
Summary of Contents for PCIe/PXIe-6302
Page 8: ...PCIe PXIe 6302 jytek com 4 Figure 3 TB 68CJ Pin Define...
Page 11: ...PCIe PXIe 6302 jytek com 7 2 3 Specification 2 3 1 Input Characteristics...
Page 14: ...PCIe PXIe 6302 jytek com 10 Table 6 Pinout defination...
Page 17: ...PCIe PXIe 6302 jytek com 13 Figure 11 Typical Noise Level 2 Figure 12 Typical Noise Level 3...
Page 18: ...PCIe PXIe 6302 jytek com 14 Figure 13 Typical Noise Level 4 Figure 14 Typical Noise Level 5...
