PCIe/PXIe-6302 |
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Figure 18 shows a random channel scan sequence, in which case the user added
some channels in random order.
Figure 18 Random channel scan sequence
When using the driver, although the scan order of the channels does not necessarily
match the order of adding channels, the data is automatically reordered internally by
the driver, so the order of the data of each channel’s reading data will always be the
same as the order of added channels.
5.2.2 ADC Timing Modes
The ADC inside 6302 has a built-in digital filter and multiple filter options. Filter
options affect the data output rate and 50 Hz / 60 Hz rejection, and the lower the
data output rate, the better the noise rejection.
The 6302 driver provides a total of 6 output data rates, from Level 0 to Level 5. Level
0 has the slowest data output rate and best noise rejection. Level 5 has the fastest
data output rate and worst noise suppression performance.
The reciprocal of the output data rate is the time required for each A /D conversion.
Table 13 describes the A /D conversion time for each data rate.
Summary of Contents for PCIe/PXIe-6302
Page 8: ...PCIe PXIe 6302 jytek com 4 Figure 3 TB 68CJ Pin Define...
Page 11: ...PCIe PXIe 6302 jytek com 7 2 3 Specification 2 3 1 Input Characteristics...
Page 14: ...PCIe PXIe 6302 jytek com 10 Table 6 Pinout defination...
Page 17: ...PCIe PXIe 6302 jytek com 13 Figure 11 Typical Noise Level 2 Figure 12 Typical Noise Level 3...
Page 18: ...PCIe PXIe 6302 jytek com 14 Figure 13 Typical Noise Level 4 Figure 14 Typical Noise Level 5...
