PCIe/PXIe-6302 |
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5.5
Trigger Source
5.5.1 Immediate Trigger
The module will acquire the signal immediately after executing the acquisition
without any trigger condition setting by default.
5.5.2 Software Trigger
The anglog acquisition task will wait in the software trigger mode until receiving a
software trigger signal from driver, then will start to acquire the data.
5.5.3 External Digital Trigger
The module supports different external digital trigger sources from PXI Trigger bus
(PXI_TRIG<0..7>), PXI_STAR and connectors of front panel (PFI). The high pulse width
of digital trigger signal must be longer then 20 ns for effective trigger. The module
will monitor the signal on digital trigger source and wait for the rising edge or falling
edge of digital signal which depends on the set trigger condition, then causes the
module to acquire the data as shown in Figure 25 below:
Figure 25 Rising and falling edges of digital signals
Learn by Example 5.5.3
Connect the K-type Thermocouple’s positive pole and negative pole to Terminal
Block’s TCO+ (Pin#35) and TCO- (Pin#1), then connect the signal source’s
positive pole and negative pole to PCIe/PXIe-6302 PFI0 (Pin#64) and GND
(Pin#30);
Set the signal source Ch1’s output to square wave (f=1Hz, Vpp=5v);
Open
Winform AI Finite Digital Trigger;
Choose
Rising
in
Trigger Condition
and choose
PFI_0
in
Trigger Source;
Set other numbers as shown and click
Start.
Summary of Contents for PCIe/PXIe-6302
Page 8: ...PCIe PXIe 6302 jytek com 4 Figure 3 TB 68CJ Pin Define...
Page 11: ...PCIe PXIe 6302 jytek com 7 2 3 Specification 2 3 1 Input Characteristics...
Page 14: ...PCIe PXIe 6302 jytek com 10 Table 6 Pinout defination...
Page 17: ...PCIe PXIe 6302 jytek com 13 Figure 11 Typical Noise Level 2 Figure 12 Typical Noise Level 3...
Page 18: ...PCIe PXIe 6302 jytek com 14 Figure 13 Typical Noise Level 4 Figure 14 Typical Noise Level 5...