72
When disabled, the chipset behaves as if it were the earlier
This item allows you to select between two methods of DRAM error checking,
ECC
and Parity (default).
This item allows you to select between three methods of memory error checking,
Auto, Enabled and Disabled
When a single bit error is detected, the offending DRAM row ID is latched . The
latched Valued is held until software explicit clears the error status flag. You can
select Enabled or Disabled.
This item determines the size of the L2 cacheability: 64MB / 512MB .
This item allows you to select between two method of chipset NA# asserted during
CPU write cycles /CPU line fills, Enabled and Disabled.
Chipset Special
Features
DRAM ECC/PARITY
Select
Memory Parity / ECC
Check
Single Bit Error Report
L2 Cache Cacheable
Size
Chipset NA# Asserted
Summary of Contents for P55XB2
Page 2: ...2...
Page 8: ...8 75 90 100 120 133 150 166 180 200 233 266 JP7 JP4 JP3 JP16 JP15 Figure 2 Jumpers location...
Page 25: ...25 75 90 100 120 133 150 166 180 200 233 266 JP7 JP4 JP3 JP16 JP15 Figure 2 Jumpers for P55XB2...
Page 37: ...37 Parallel port is a 25 pins female external DB25 connector for parallel port PCI Parallel...
Page 88: ...88 MMX 200...