
65
Enabled
Video shadow is enabled
Disabled
Video shadow is disabled
These categories determine whether option ROMs
will be copied to RAM. An example of such option ROM would be support of on-
board SCSI.
Enabled
Optional shadow is enabled
Disabled
Optional shadow is disabled
3.4 Chipset Features Setup
ROM PCI/ISA BIOS (XXXXXXXX)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
DRAM Timing
DRAM RAS# Precharge Time
DRAM Read Burst (EDO/FP)
Esc : Quit
F1 : Help
(Shift)F2 :Change Color
: Select Item
Fast RAS To CAS Delay
ISA Bus Clock
Refresh RAS# Assertion
SDRAM (CAS Lat/RAS-toCAS)
8 bit I/O Recovery Time
Video BIOS Cacheable
Fast MA to RAS# Delay CLK
DRAM Write Burst Timing
PU/PD/+/- : Modify
DRAM R/W Leadoff Timing
Fast EDO Path Select
System BIOS Cacheable
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Enabled
60 ns
PCICLK/4
5 Clks
3/3
1
Enabled
1
x333
6
Disabled
Disabled
1
4
3
x222/x333
Delay Transaction
: Disabled
F5 : Old Values
F7 : Load Setup Defaults
16 bit I/O Recovery Time
Peer Concurrency
Memory Hole At 15M-16M
Passive Release
:
:
:
Enabled
Disabled
Enabled
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
C8000 - CBFFF DC000
- DFFFF
Summary of Contents for P55XB2
Page 2: ...2...
Page 8: ...8 75 90 100 120 133 150 166 180 200 233 266 JP7 JP4 JP3 JP16 JP15 Figure 2 Jumpers location...
Page 25: ...25 75 90 100 120 133 150 166 180 200 233 266 JP7 JP4 JP3 JP16 JP15 Figure 2 Jumpers for P55XB2...
Page 37: ...37 Parallel port is a 25 pins female external DB25 connector for parallel port PCI Parallel...
Page 88: ...88 MMX 200...