IWILL P55XB2, Manual, Page: 67 / 91

67
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered
if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
Pre-defined values for DRAM, cache.. timing according to CPU type & system clock.
The Choice: Enabled, Disabled.
Note: When this item is enabled, the pre-defined items will become SHOW-
ONLY.
The DRAM timing is controlled by the DRAM Timing Registers. The timings
programmed into this register are dependent on the system design. Slower rates may
be required in certain system designs to support loose layouts or slower memory.
60ns DRAM Timing Type.
70ns DRAM Timing Type.
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is
refreshed entirely as the result of a single request. This option allows you to
determine the number of CPU clocks allocated for the
R
ow
A
ddress
S
trobe to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed,
refresh may be incomplete and data lost.
3 Three clocks.
4 Four clocks.
Four clocks is the default.
Auto Configuration
DRAM Timing
DRAM RAS#
Precharge Time