REL0.1
Page 13 of 95
Kintex Ult FPGA SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
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Data UART x 2 Port
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I2C x 2 Ports
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JTAG x1 Port
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Up to 2 SerDes lanes for high-speed peripheral interfaces (PCIe, SATA, SGMII)
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10 GPIOs From LS1021A
From KU19P
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FPGA IOs - HP Bank 65,66
➢
Up to 24 LVDS IOs/52 Single ended (SE) IOs
o
Up to 4 GC Global Clock Input pins (LVDS/SE)
o
Up to 16 ADC Input pins (Differential/Single Ended)
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FPGA IOs - HP Bank 67
➢
Up to 22 LVDS IOs/44 Single ended (SE) IOs
o
Up to 4 GC Global Clock Input pins (LVDS/SE)
o
Up to 15 ADC Input pins (Differential/Single Ended)
Board to Board Connector3 Interfaces (240pin)
From KU19P
•
GTY High Speed Transceivers (up to 32.75Gbps) x 20
1
Board to Board Connector4 Interfaces (80pin)
From KU19P
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GTY High Speed Transceivers (up to 32.75Gbps) x 4
General Specification
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Power Supply
:
5V (from Board-to-Board Connector2)
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Form Factor
:
110mm x 75mm
1
In Board-to-Board Connector3, by default one GTY transceiver link is connected with on-SOM PCIe transceiver.
