iWave iW-RainboW-G22D, Hardware User'S Manual, Page: 42 / 71

REL1.1
Page 42 of 71
iWave Systems Technologies Pvt. Ltd.
RZ/G1E SODIMM Development Platform Hardware User Guide
Table 9: Camera Connector Pin Out
Pin
No
Pin Name Signal Name
Signal Type/
Termination
Description
1 STROBE STROBE - NC.
2 AGND AGND Power Analog Ground.
3 SIOD I2C5_SDA(GP0_15) IO, 3.3V OD I2C5 Data Signal.
4 AVDD AVDD O, 3.3V Power 3.3V Analog Supply Voltage.
5 SIOC I2C5_SCL(GP0_14) O, 3.3V OD I2C5 Clock Signal.
6 RESETB GPIO33/GP4_27 O, 3.3V CMOS Reset Output, Active Low.
7 VSYNC VI1_VSYNC(GP5_23) I, 3.3V CMOS Camera vertical synchronization signal.
8 PWDN ETH_TXD0/VI1_CLKENB
(GP5_20) O, 3.3V CMOS Active high Camera Power Down.
Connected to GND to enable the camera
always.
9 HSYNC VI1_HSYNC(GP5_22) I, 3.3V CMOS Camera horizontal synchronization signal.
10 DVDD DVDD O, 1.8V Power 1.8V Digital Supply Voltage.
11 DOVDD DOVDD O, 3.3V Power 3.3V IO Supply Voltage.
12 D9 ETH_INT/EXP_VI1_DAT
A7(GP5_19) I, 3.3V CMOS Camera Data7.
13 XCLK CSI_MCLK1 O, 3.3V CMOS Camera Reference Clock. Connected to on-
board 26MHz Oscillator.
14 D8 ETH_TX_EN/VI1_DATA
6(GP5_18) I,3.3V CMOS Camera Data6.
15 DGND DGND Power Digital Ground.
16 D7 ETH_TXD1/VI1_DATA5(
GP5_17) I, 3.3V CMOS Camera Data5.
17 PCLK ETH_CRS_DV/VI1_CLK(
GP5_11) I, 3.3V CMOS Camera Pixel Clock.
18 D6 ETH_REF_CLK/VI1_DAT
A4(GP5_16) I, 3.3V CMOS Camera Data4.
19 D2 MSIOF1_SCK/VI1_DAT
A0¹ I, 3.3V CMOS Camera Data0.
Note: Same pin optionally connected to
Expansion connector J12 pin13 through
resistor and default not populated.
20 D5 MSIOF1_RXD/VI1_DAT
A3¹ I, 3.3V CMOS Camera Data3.
Note: Same pin optionally connected to
Expansion connector J12 pin14 through
resistor and default not populated.
21 D3 MSIOF1_SS1/VI1_DATA
1¹ I, 3.3V CMOS Camera Data1.
Note: Same pin optionally connected to
Expansion connector J12 pin17 through
resistor and default not populated.