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Intel Cyclone 10 GX FPGA, User Manual

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Intel Cyclone 10 GX FPGA User Manual Download Page 16

Bank Number

Function

I/O Type

I/O Count

Description

1C/1D

PCIE_RX [0:3]

CML/LVDS input

8(4p)

PCIe Gen2 Receive

1D

SFP+_TX [0:1]

CML output

4(2p)

SFP+ Transmit

1D

SFP+_RX [0:1]

CML / LVDS input

4(2p)

SFP+ Receive

1D

USB31_TX

CML output

2(1p)

USB3.1 Trasnsmit

1D

USB31_RX

CML/LVDS input

2(1p)

USB3.1 Receive

1C/1D

FMC_DP_C2M [0:4]

CML output

10(5p)

FMC Transmit

1C/1D

FMC_DP_M2C [0:4]

CML/LVDS input

10(5p)

FMC Receive

Global FPGA Clocks

2A

M10_USB_CLK

1.8 V CMOS input

1

30/48 MHz from U2

(MAX10)

2A

C10_REFCLK1

LVDS input

2

125 MHz (adjustable)

2L

C10_CLK50M

1.8 V CMOS input

1

50 MHz OSC, free

running

2L

C10_REFCLK2

LVCMOS input

2

100 MHz (adjustable)

2J

REFCLK_EMIF

LVDS input

2

21.186 MHz

(adjustable)

Global FPGA Reset

2A

FPGA_RESETn

1.8 V CMOS input

1

From U2 (Intel MAX

10)

JTAG

CSS

C10_TCK

1.8 V CMOS input

1

From U2 (Intel MAX

10)

CSS

C10_TMS

1.8V CMOS input

1

From U2 (Intel MAX

10)

CSS

C10_TDI

1.8 V CMOS input

1

From U2 (Intel MAX

10)

CSS

C10_TDO

1.8 V CMOS input

1

To U2 (Intel MAX 10)

Configuration

2A

C10_CLKUSR

1.8 V CMOS input

1

100 MHz, for

calibration

CSS

C10_MSEL[0:1]

1.8 V CMOS input

2

From DIP Switch S1

CSS

C10_nSTATUS

1.8 V CMOS output

1

To U2/U3 (Intel MAX

10)

CSS

C10_CONF_DONE

1.8 V CMOS output

1

To U2/U3 (Intel MAX

10)

CSS

C10_nCONFIG

1.8 V CMOS input

1

From U2 (Intel MAX

10)

CSS

C10_CS0n

1.8 V CMOS output

1

To U4 (EPCQ-L)

CSS

C10_AS_D [0:3]

1.8 V CMOS inout

4

To U4 (EPCQ-L)

CSS

C10_DCLK

1.8 V CMOS inout

1

To U4 (EPCQ-L) for

ASx4

continued...   

4 Development Board Components

UG-20105 | 2017.12.18

Intel

®

 Cyclone

®

 10 GX FPGA Development Kit User Guide

16

Summary of Contents for Cyclone 10 GX FPGA

Page 1: ...Intel Cyclone 10 GX FPGA Development Kit User Guide Subscribe Send Feedback UG 20105 2017 12 18 Latest document on the web PDF HTML ...

Page 2: ...4 5 1 Switches 23 4 5 2 Pushbuttons 24 4 5 3 LEDs 25 4 6 Clocks 26 4 7 Memory 27 4 7 1 EMIF with DDR3 27 4 7 2 QSPI Flash 27 4 8 Power 27 4 9 Transceivers Interfaces and Communication Ports 29 4 9 1 Transceiver Channels 29 4 9 2 PCIe Interface 29 4 9 3 SFP Interface 29 4 9 4 USB3 1 Type C Interface 30 4 9 5 FPGA Mezzanine Card FMC Interface 32 4 9 6 10 100 1000Base T Ethernet Connector 37 4 9 7 I2...

Page 3: ...ormation 60 A 1 Safety and Regulatory Information 60 A 1 1 Safety Warnings 61 A 1 2 Safety Cautions 62 A 2 Compliance and Conformity Statements 64 B Revision History 65 B 1 User Guide Revision History 65 Contents Intel Cyclone 10 GX FPGA Development Kit User Guide 3 ...

Page 4: ...ator LVDS for tranceivers 644 53125 MHz by default LVDS to FPGA tranceiver Programmable clock generator for FPGA logic 21 186 MHz LVDS for EMIF LVDS to FPGA core 125 MHz LVDS for transceiver of USB3 1 LVDS to FPGA transceiver 125 MHz for Gigabit Ethernet LVDS to FPGA core 100 MHz for FPGA logic LVCMOS to FPGA core 100 MHz for PCIe system to FPGA transceiver UG 20105 2017 12 18 Intel Corporation Al...

Page 5: ...DR3 933 MHz Communication Ports 10 100 1000Base T Ethernet port with SGMII LVDS USB3 1 Type C supporting SuperSpeed backward compatible with USB2 0 2 SFP supporting 10GE FMC expansion card 12G SDI Semtech RDK 12GSRD ALTRA00 Evaluation Board 8G DisplayPort Bitec FMC DisplayPort Daughter Card 6G HDMI 2 0 Bitec FMC HDMI Daughter Card Pushbuttons 3 User Push Buttons 1 User Program selecting Pushbutton...

Page 6: ...ht x 7 Length Operating Environment Ambient Temperature 0 C to 45 C 1 2 Recommended Operating Conditions Recommended ambient operating temperature range 0 C to 45 C Maximum ICC load current 6 Amp Maximum ICC load transient percentage 30 Maximum board power consumption 75 Watts 1 3 Handling the Board When handling the board it is important to observe static discharge precautions Note Without proper...

Page 7: ... Prime Pro Edition is optimized to support the advanced features in Intel s next generation FPGAs and SoCs The Intel Cyclone 10 GX FPGA is only supported on Intel Quartus Prime Pro Edition There is no paid license fee required for Intel Cyclone 10 GX support in Intel Quartus Prime Pro Edition Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software Nios II EDS and the M...

Page 8: ...ign files Use these files as a starting point for a new prototype board design demos Contains demonstration applications when available documents Contains the development kit documentation examples Contains the sample design files for the development kit factory_recovery Contains the original data programmed onto the board before shipment Use this data to restore the board with its original factor...

Page 9: ... the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions 2 Getting Started UG 20105 2017 12 18 Intel Cyclone 10 GX FPGA Development Kit User Guide 9 ...

Page 10: ... the default factory switch settings for the Intel Cyclone 10 GX FPGA Development Kit Table 2 DIP Switch Settings Board Label Switch Default Position Function S1 S1 1 OPEN OFF 1 Intel Cyclone 10 GX GX FPGA MSEL S1 2 OPEN OFF 1 S2 S2 1 CLOSE ON 0 Select clock from Si570 for Si53307 s output S2 2 OPEN OFF 1 Enable the output of Si570 S3 S3 1 CLOSE ON 0 Select internal oscillator as the PLL reference...

Page 11: ...ned S6 2 OPEN OFF 1 Reserved no function defined S9 S9 1 OPEN OFF 1 User available Digital Input 0 S9 2 OPEN OFF 1 User available Digital Input 1 S15 S15 1 OPEN OFF 1 User available Digital Input 2 S15 2 OPEN OFF 1 User available Digital Input 3 3 Development Kit Setup UG 20105 2017 12 18 Intel Cyclone 10 GX FPGA Development Kit User Guide 11 ...

Page 12: ...erals Configuration with Intel MAX 10 FPGA Timing Power Supply Table 3 Board Components Table Board Reference Type Description Featured Devices U1 FPGA Intel Cyclone 10 GX FPGA 10CX220YF780E5G 220K Logic Elements 12 Transceivers F780 BGA package continued UG 20105 2017 12 18 Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words ...

Page 13: ...uctor implements 1 03V 1 5V and 1 8V power rails to FPGA U56 Voltage Regulator Enpirion EN6347QI 4A PowerSoC Voltage Mode Synchronous PWM Buck with Integrated Inductor implements voltage adjustable power rail to FPGA and FMC daughter card U62 Voltage Regulator Enpirion ER3110DI 1A Wide VIN Synchronous Buck Regulator implements power supply used by U2 and U3 Configuration and Setup Elements J9 Embe...

Page 14: ... Programmable Oscillator Programmable Oscillator for Intel Cyclone 10 GX FPGA Transceivers LVDS U7 Clock Buffer 2 1 buffer for reference clock U64 Programmable clock generator Eight channel Programmable clock generator 4 outputs are implemented default frequencies are 125 MHz 21 186 MHz 125 MHz and 100 MHz Transceiver Interfaces U16 PCIe x4 Golden Finger PCIe Gen2 x4 endpoint J5 J6 SFP Support 10 ...

Page 15: ...ps Transceiver 12 GPIO 284 LVDS Pair 118 PCIe Hard IP Block 1 Hard Memory Interfaces 2 Package F780 29 mm x 29 mm The table below presents a summary of the Intel Cyclone 10 GX FPGA I O resource allocation I O Direction is with respect to the FPGA Table 5 Cyclone 10 GX FPGA I O Resources Table Bank Number Function I O Type I O Count Description Transceiver Clocks 1C USB_REFCLK 2 125 MHz adjustable ...

Page 16: ...MHz adjustable Global FPGA Reset 2A FPGA_RESETn 1 8 V CMOS input 1 From U2 Intel MAX 10 JTAG CSS C10_TCK 1 8 V CMOS input 1 From U2 Intel MAX 10 CSS C10_TMS 1 8V CMOS input 1 From U2 Intel MAX 10 CSS C10_TDI 1 8 V CMOS input 1 From U2 Intel MAX 10 CSS C10_TDO 1 8 V CMOS input 1 To U2 Intel MAX 10 Configuration 2A C10_CLKUSR 1 8 V CMOS input 1 100 MHz for calibration CSS C10_MSEL 0 1 1 8 V CMOS inp...

Page 17: ...om U2 Intel MAX 10 2A M10_USB_Oen 1 8 V CMOS input 1 From U2 Intel MAX 10 2A M10_USB_SCL 1 8 V CMOS input 1 From U2 Intel MAX 10 2A M10_USB_SDA 1 8 V CMOS inout 1 From U2 Intel MAX 10 EMIF 2J DDR3_A 0 14 1 5 V SSTL output 15 To U12 U13 U14 DDR3 2J DDR3_BA 0 2 1 5 V SSTL output 3 To U12 U13 U14 DDR3 2J DDR3_RASn 1 5 V SSTL output 1 To U12 U13 U14 DDR3 2J DDR3_CASn 1 5 V SSTL output 1 To U12 U13 U14...

Page 18: ...2 To U33 88E1111 PHY AC 2L ETH_MDC_C10 1 8 V CMOS output 1 To U33 88E1111 PHY 2L ETH_MDIO_C10 1 8 V CMOS inout 1 To U33 88E1111 PHY AC 2L ETH_INTn_C10 1 8 V CMOS input 1 To U33 88E1111 PHY AC 2L ETH_RESETn_C10 1 8 V CMOS output 1 To U33 88E1111 PHY AC SFP sideband 2L SFP_SCL_0 1 8 V CMOS output 1 To J5 SFP 0 2L SFP_SDA_0 1 8 V CMOS inout 1 To J5 SFP 0 2L SFP_INT_0 1 8 V CMOS input 1 To J5 SFP 0 2L...

Page 19: ... U26 USB3 1 Transceiver Switch 2L USB_ID_1 8V 1 8 V CMOS input 1 To U26 USB3 1 Transceiver Switch QSPI Flash 2L C10_QSPI_CSn 1 8 V CMOS output 1 To U58 QSPI Flash 2L C10_QSPI_RESETn 1 8 V CMOS output 1 To U58 QSPI Flash 2L C10_QSPI_CLK 1 8 V CMOS output 1 To U58 QSPI Flash 2L C10_QSPI_D 0 3 1 8 V CMOS inout 4 To U58 QSPI Flash 4 3 MAX 10 System Controller The highlights of the Intel MAX 10 devices...

Page 20: ...ention Multiple interface option Embedded multiplier blocks One 18 18 or two 9 9 multiplier modes Cascadable blocks enabling creation of filters arithmetic functions and image processing pipelines ADC 12 bit successive approximation register SAR type Up to 16 analog inputs Cumulative speed up to 1 million samples per second MSPS Integrated temperature sensing capability Clock networks Global clock...

Page 21: ...cro USB type B connector J9 Figure 3 JTAG topology block diagram System Intel MAX 10 FPGA USB PHY CY7C68013 HDR2X5 for System Intel MAX 10 FPGA FMC Configuration Intel MAX 10 FX2 Bus 3 3 V PD 3 0 JTAG 3 3 V Intel Cyclone 10 FPGA JTAG 1 8 V USB Configuration 1 8 V JTAG 3 3 V JTAG 3 3 V The system Intel MAX 10 device itself can be configured through on board USB port or an external USB Blaster II he...

Page 22: ...EL0 MSEL2 is tied to GND ON 0 S1 2 C10_MSEL1 Figure 4 FPGA Configuration Scheme Block Diagram Intel Cyclone 10 GX FPGA DIPswitch S1 Intel MAX 10 10M08SAU169 SYS UBII Intel MAX 10 10M08SAU169 PFL EPCQ L NOR Flash X32 MSEL nSTATUS nCONFIG CONF_DONE FPP X16 DCLK AS X4 The Intel Cyclone 10 GX FPGA device is configured with two modes ASx4 or FPP x16 The AS x4 mode uses an EPCQ L 1024 to store the image...

Page 23: ...Select program S12 SYS_CONFIG_PB Reconfigure D16 PGM_LED0 PGM_LED 2 0 indicates the program to be used D17 PGM_LED1 D18 PGM_LED2 Side Bus A group of Side Bus signals are defined between Intel MAX 10 and Intel Cyclone 10 GX FPGA device to provide a higher speed access through on board USB Blaster This interface is reserved in harwdare 4 5 Status and User I O Elements 4 5 1 Switches Power Switch The...

Page 24: ...0 values 00 internal oscillator 10 external reference input from SMB Set to 00 by default S3 2 Si5340_INSEL1 0 S2 S2 1 CLKBUF_SEL 0 Set the input source of Si53307 0 Use CLKIN0 1 Use CLKIN1 Fixed to 0 S2 2 Si570_OE 1 Enable the output of Si570 Y2 0 Output disabled 1 Output enabled Fixed to 1 S5 S5 1 FMC_JTAGEN 1 Enable FMC Card JTAG 0 Isolate FMC card JTAG from the chain 1 Add FMC Card JTAG into t...

Page 25: ...d 4 5 3 LEDs The LEDs are on the top side of the board at the upper right corner Table 13 Board LED Definition Board Reference Signal Name Colour Function D16 PGM_LED0 Green Image 0 is loaded in FPP mode D17 PGM_LED1 Green Image 1 is loaded in FPP mode D18 PGM_LED2 Green Image 2 is loaded in FPP mode D14 LOAD_LED Green Indicates image is loading D15 CFGDONE_LED Green Indicates image loading succee...

Page 26: ...ce clock at frequency up to 725 MHz is available for Intel Cyclone 10 GX FPGA Transceiver Other clocks are generated with an programmable clock generator Si5332 at I2C address 7 b110_1010 Features of Si5332 Output frequency Range 5 MHz to 312 5 MHz differential Input frequency Range 10 MHz to 250 MHz differential 16 MHz to 30 MHz external crystal Embedded 50 MHz crystal option for 8 or 12 port dev...

Page 27: ...nted with DDR3 devices The EMIF uses continuous banks in the same column To achieve 933 MHz speed EMIF uses bank 2J and 2K to support 40 bit width at 933 MHz The signal definition conforms to the EMIF constraints 4 7 2 QSPI Flash Besides the flash memories used by the configuration modules a user accessible QSPI Flash device is provided for non volatile data storage The device is 256 Mb with 4 bit...

Page 28: ...ctor 12V_ATX PCIe_12V 12V_IN 12 V FPGA Power UP Sequencing VCC VCCP VCCERAM VCCR VCCT VCCH VCCA_PLL VCCPT VCCBAT VCCPGM VCCIO 1 2 3 4 FPGA Quick Power DOWN Sequencing 1 2 3 4 12 V Adaptor EM2130_5V ER2120 USB_5V 1 5 A EN6337QI IO_1 8V 1 A EN6337QI C10_1 8V 1 6 A EN6337QI C10_0 95V 1 6 A EM2130H 3 3 V 12 A EM2130L 0 9 V 18 A ER3105 Table 14 Enpirion Power Regulators Power Group Power Rail Generated...

Page 29: ...ace is configured to End Point The PCIe interface has the following signals Transceivers x4 up to 5 Gbps PCIE_REFCLKp n 100 MHz from PCIe system PCIE_SMBUS 3 3V level translated to 1 8V with U18 PCIE_PERSTn 3 3V level translated to 1 8V with U17 PCIE_WAKEn 3 3V level translated to 1 8V with U17 reserved The PCIe width can be selected with Jumper resistors R506 installed x1 mode R507 installed x4 m...

Page 30: ...mber Signal I O Type Function P0 SFP_RLED Output Red LED indicates LOS ERR 0 ON P1 SFP_GLED Output Green LED indicates Link 0 ON P2 SFP_TXDIS Output Tx_Disable Pulled up Transmitter is turned off if high P3 SFP_TFLT Input Tx_Fault Pulled up indicates fault when high P4 SFP_RS1 Output Rate Select Pulled up with 1K resistor P5 SFP_RLOS Input Rx_LOS Pulled up indicates LOS when high P6 SFP_RS0 Output...

Page 31: ...ort mode is Dual Role Port DRP by default It can be chnaged to DFP if R177 is installed or UFP if R178 is installed Current Advertisement is 1 5A A USB3 1 Redriver TUSB1002 is used to condition the high speed signal because of the degradation caused by the 2 1 mux and to support the 10 Gbps SuperSpeed Plus The equalization gain and VOD gain of TUSB1002 are set by resistors The default settings are...

Page 32: ...l V57 1 Name Signal Name Pin Number SDI FMC Signal Name DisplayPort FMC Signal Name HDMI FMC Signal Name FMC_DP_C2M_ P0 DP0_C2M_P DP0_C2M_P C2 x FMC_TX_P0 GXB_TXp0 FMC_DP_C2M_ N0 DP0_C2M_N DP0_C2M_N C3 x FMC_TX_N0 GXB_TXn0 FMC_DP_C2M_ P1 DP1_C2M_P DP1_C2M_P A22 x FMC_TX_P1 GXB_TXp1 FMC_DP_C2M_ N1 DP1_C2M_N DP1_C2M_N A23 x FMC_TX_N1 GXB_TXn1 FMC_DP_C2M_ P2 DP2_C2M_P DP2_C2M_P A26 FMC_GS12181 _IN FM...

Page 33: ...N DP2_M2C_N A7 FMC_GS12141 _OUT FMC_RX_N2 GXB_RXn2 FMC_DP_M2C_ P3 DP3_M2C_P DP3_M2C_P A10 x FMC_RX_P3 x FMC_DP_M2C_ N3 DP3_M2C_N DP3_M2C_N A11 x FMC_RX_N3 x FMC_DP_M2C_ P4 DP4_M2C_P DP4_M2C_P A14 x x x FMC_DP_M2C_ N4 DP4_M2C_N DP4_M2C_N A15 x x x X DP5_M2C_P DP5_M2C_P A18 x x x X DP5_M2C_N DP5_M2C_N A19 x x x X DP6_M2C_P DP6_M2C_P B16 x x x X DP6_M2C_N DP6_M2C_N B17 x x x X DP7_M2C_P DP7_M2C_P B12...

Page 34: ...0 G10 x x x FMC_LA_TXP1 LA04_P LA_TX_P1 H10 FMC_GS12141 _GPIO2 x x FMC_LA_TXN1 LA04_N LA_TX_N1 H11 FMC_GS12141 _GPIO3 x x FMC_LA_TXP2 LA05_P LA_TX_P2 D11 x x x FMC_LA_TXN2 LA05_N LA_TX_N2 D12 x x x FMC_LA_RXP1 LA06_P LA_RX_P1 C10 x x x FMC_LA_RXN1 LA06_N LA_RX_N1 C11 x x x FMC_LA_TXP3 LA07_P LA_TX_P3 H13 FMC_GS12181 _GPIO0 x x FMC_LA_TXN3 LA07_N LA_TX_N3 H14 FMC_GS12181 _GPIO1 x x FMC_LA_RXP2 LA08...

Page 35: ...N_CC LA_TX_N8 D21 x x x FMC_LA_RXP7 LA18_P_CC LA_RX_P7 C22 x x x FMC_LA_RXN7 LA18_N_CC LA_RX_N7 C23 x x x FMC_LA_TXP9 LA19_P LA_TX_P9 H22 FMC_LMH1983 _NO_ALIGN AUX_RX_DRV_ OE_FMC x FMC_LA_TXN9 LA19_N LA_TX_N9 H23 FMC_LMH1983 _NO_LOCK AUX_RX_DRV_ IN_FMC x FMC_LA_RXP8 LA20_P LA_RX_P8 G21 FPGA_STATUS1 TX_SCL_FMC DVI_RX_HPD_ N FMC_LA_RXN8 LA20_N LA_RX_N8 G22 x RX_SENSE_N_I NV_FMC DVI_RX_SDA FMC_LA_TXP...

Page 36: ...1 FMC_FPGA_VS YNCn HDCP_SCL x FMC_LA_TXN1 4 LA28_N LA_TX_N14 H32 FMC_FPGA_HS YNCn HDCP_SDA x FMC_LA_RXP1 2 LA29_P LA_RX_P12 G30 tp x x FMC_LA_RXN1 2 LA29_N LA_RX_N12 G31 x x x FMC_LA_TXP15 LA30_P LA_TX_P15 H34 LMK03328_PD N PU 3 3V x x FMC_LA_TXN1 5 LA30_N LA_TX_N15 H35 FMC_GSPI_CS _GS12181 x x FMC_LA_RXP1 3 LA31_P LA_RX_P13 G33 x x x FMC_LA_RXN1 3 LA31_N LA_RX_N13 G34 x x x FMC_LA_TXP16 LA32_P LA...

Page 37: ...rnet PHY The interface to FPGA is with SGMII through a pair of LVDS on FPGA The PHY is managed with MDC MDIO management interface The signals used and hardware configuration pins of the Marvell device are shown in the table below Table 18 JTAG DIP Switch Settings Hardware Configuration Pins Connection Bits Bit 2 Bit 1 Bit 0 Config0 GND 000 PHYADR 2 0 000 Config1 GND 000 ENA_PAUSE 0 PHYADR 4 3 00 C...

Page 38: ...e Marvell 88E1111 device can be changed with MDC MDIO The MDC MDIO is connected to the FPGA device through a level translator 4 9 7 I2C PMBUS The power and various peripherals are managed by I2C PMBUS The topology of the I2C bus is shown in the figure below 4 Development Board Components UG 20105 2017 12 18 Intel Cyclone 10 GX FPGA Development Kit User Guide 38 ...

Page 39: ...0 Si570 110_0110 I2C 1 8 V Level Shifter Intel Cyclone 10 FPGA SFP 1 101_0000 101_0001 I O Expander 010_0000 I2C 1 8 V Level Shifter I2C 3 3 V USB 3 1 Switch 110_0111 I2C 1 8 V Level Shifter 3 3 V SFP 1 101_0000 101_0001 I O Expander 010_0000 I2C 1 8 V Level Shifter I2C 3 3 V FMC Daughter Card User Defined I2C 1 8 V Level Shifter 3 3 V I2C 2 5 V 4 Development Board Components UG 20105 2017 12 18 I...

Page 40: ...actory configuration Figure 9 BTS GUI UG 20105 2017 12 18 Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel s...

Page 41: ...se the BTS The BTS relies on the Intel Quartus Prime software s specific library Before running the BTS open the Intel Quartus Prime software to automatically set the environment variable QUARTUS_ROOTDIR The BTS uses this environment variable to locate the Intel Quartus Prime library The version of Intel Quartus Prime software set in the QUARTUS_ROOTDIR environment variable should be newer than ve...

Page 42: ...est_system directory and run the BoardTestSystem exe application 2 A GUI appears displaying the application tab corresponding to the design running in the FPGA If the design loaded in the FPGA is not supported by the BTS GUI you will receive a message prompting you to configure your board with a valid BTS design Refer to the Configure Menu on configuring your board Note If some design is running i...

Page 43: ... begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled If you use the Intel Quartus Prime Programmer for configuration rather than the BTS GUI you may need to restart the GUI 5 3 2 The System Info Tab The System Info tab shows the board s current configuration The tab displays the contents of the Intel MAX 10 registers the JTAG chain the b...

Page 44: ...ndicates MAC Address of the board System MAX Control MAX Ver Indicates the vesion of Intel MAX 10 code currently running on the board The Intel MAX 10 code resides in the package dir examples max10 directory Newer revisions of this code may be available on the Intel Cyclone 10 GX FPGA Development kit link on the Intel website The Intel MAX 10 register control allows you to view and change the curr...

Page 45: ...iguration PSS Displays the Intel MAX 10 PSS register value Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration JTAG Chain The JTAG chain shows all the devices currently in the JTAG chain Note System MAX and FPGA should all be present in the JTAG chain when running BTS GUI 5 3 3 The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O c...

Page 46: ...he board user push buttons Press a push button on the board to see the graphical display change accordingly Qsys Memory Map The Qsys memory map control shows the memory map of the bts_config sof design running on your board 5 3 4 The EPCQ Tab The EPCQ tab allows you to read and write EPCQ flash memory on your board The memory table displays the address 0 contents by default after you configure the...

Page 47: ...sh memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents Random Starts a random data pattern test to flash memory limited to the 512K test system scratch page Increase Starts an incrementing data pattern test to flash memory limited to the 512K test system scratch page Erase Erases flash memory of the current sector Flash Memory Map D...

Page 48: ...ced or not synced state The pattern is considered synced when the start of the data sequence is detected Details Shows the PLL lock pattern sync status and number of errors for a single channel Port Allows you to specify which interface to test The following port tests are available 5 Board Test System UG 20105 2017 12 18 Intel Cyclone 10 GX FPGA Development Kit User Guide 48 ...

Page 49: ...is on the second pre tap of the transmitter buffer 1st post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer 2nd post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer Equalizer Specifies the AC gain setting for the receiver equalizer in four stage mode DC gain Specifies the DC gain setting for the receiver equalizer in four s...

Page 50: ...erted into the transmit data stream Insert Inserts a one word error into the transmit data stream each time you click the button Insert is only enabled during transaction performance analysis Clear Resets the Detected errors and Inserted errors counters to zeroes Run Control Start Initiates the selected ports transaction performance analysis Note Always click Clear before Start Stop Terminates tra...

Page 51: ...k Shows the PLL locked or unlocked state Pattern Sync Shows the pattern synced or not synced state The pattern is considered synced when the start of he data data sequence is detected Details Shows the PLL lock pattern sync status and number of errors per channel 5 Board Test System UG 20105 2017 12 18 Intel Cyclone 10 GX FPGA Development Kit User Guide 51 ...

Page 52: ...ecifies the amount of pre emphasis on the second pre tap of the transmitter buffer 1st post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer 2nd post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer Equalizer Specifies the AC gain setting for the receiver equalizer in four stage mode DC gain Specifies the DC gain setting for ...

Page 53: ...to the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected error and Inserted error counters to zeroes Run Control Start Initiates the selected ports transaction performance analysis Note Always click Clear before Start Stop Terminates t...

Page 54: ...nformation collected since you last clicked Start Write Read and Total performance bars Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve Write MBps Read MBps and Total MBps Show the number of bytes of data analayzed per second Error Control This control displays data errors detected during analysis and allows you to insert errors 5 Board Tes...

Page 55: ...Monitor measures and reports current power information and communicates with the Intel MAX 10 device on the board through the JTAG bus A power monitor circuit attached to the Intel MAX 10 device allows you to measure the power that the FPGA is consuming To start the application click the Power Monitor icon in the BTS You can also run the Power Monitor as a stand alone application The PowerMonitor ...

Page 56: ...ent maximum and minimum numerical power readings in mA Table Displays real time values of power rails It refreshes about every 10 seconds When you click some rail the power rail will show on the Graph Chart Configuration Speed Adjustment Specifies how often to refresh the graph Date Record Record real time voltage current and power values and save to a log file Reset Clears the graph resets the mi...

Page 57: ...to the Intel MAX 10 device through a 2 wire serial bus Figure 20 Clock Controller Si570 Serial Port Registers Shows the current values from the Si570 registers for frequency configuration Target Frequency MHz Allows you to specify the frequency of the clock Legal values are between 10 MHz and 725 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possi...

Page 58: ...r the programmable oscillators Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this period Intel recommends resetting the FPGA logic after changing frequencies Figure 21 Clock Controller Si5332 Si5332 tab displays the same GUI controls for each clock generators The Si5332 is a high performance low jitter clock generator capabale of synthe...

Page 59: ...e divider mode and value currently being used on this board Disable Allows you to disable a single output Read Reads the current frequency setting for the oscillator Set Sets the programmable oscillator frequency for the selected clock to the value in OUT0 OUT1 OUT4 OUT6 and OUT7 controls for the Si5332 Frequency changes might take several milliseconds to take effect You might see glitches on the ...

Page 60: ...t operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47 Safety Assessment and CE mark requirements have been completed however other certifications that may be required for installation and operation in your region have not been obtained UG 20105 2017 12 18 Intel Corporation All rights reserved Intel the Inte...

Page 61: ...ed to remove all DC power from the board system The socket outlet must be installed near the equipment and must be readily accessible System Grounding Earthing To avoid shock you must ensure that the power cord is connected to a properly wired and grounded receptacle Ensure that any equipment to which this product will be attached is also connected to properly wired and grounded receptacles A Addi...

Page 62: ...t during an electrical storm Risk of Fire To reduce the risk of fire keep all flammable materials a safe distance away from the boards and power supply You must configure the development kit on a flame retardant surface A 1 2 Safety Cautions Caution Hot Surfaces and Sharp Edges Integrated Circuits and heat sinks may be hot if the system has been running Also there might be sharp edges on some boar...

Page 63: ...harmful interference to radio communications If this equipment does cause harmful interfence to radio or television reception which can be determined by turning the equipment on and off the user is required to take measures to eliminate this interference Telecommunications Port Restrictions The wireline telecommunications ports modem xDSL T1 E1 on this product must not be connected to the Public S...

Page 64: ...t in unsorted municipal waste A 2 Compliance and Conformity Statements CE EMI Conformity Caution This development board is delivered conforming to relevant standards mandated by Directive 2014 30 EU Because of the nature of programmable logic devices it is possible for the user to modify the development kit in such a way as to generate electromagnetic interference EMI that exceeds the limits estab...

Page 65: ...ance of its FPGA and semiconductor products to current specifications in accordance with Intel s standard warranty but reserves the right to make changes to any products and services at any time without notice Intel assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Intel In...

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