Intel ARM Cortex-A9, Introduction Manual

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I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
As shown in Table 4, the exception vector table must occupy the fixed memory locations in the address range 0x000
to 0x01C. Each word in this table must be an instruction that causes the program execution to go to the corresponding
exception-service routine. This requires the program counter to be loaded with the address of the first instruction in
the exception-service routine. This can be accomplished with load instructions
LDR PC, =EXCEPTION_SERVICE_ROUTINE_NAME
Figure 5 illustrates the structure of the code that can be used.
. text
. global _start
LDR PC, =_start /* Go to the beginning of the MAIN program. */
LDR PC, =SERVICE_UND /* Unimplemented instruction. */
LDR PC, =SERVICE_SVC /* Software interrupt. */
LDR PC, =SERVICE_ABT_INST /* Failed instruction access. */
LDR PC, =SERVICE_ABT_DATA /* Failed data access. */
. word 0 /* Null entry for address 0x014. */
LDR PC, =SERVICE_IRQ /* Hardware IRQ interrupt. */
LDR PC, =SERVICE_FIQ /* Hardware FIQ interrupt. */
/* The main program. */
_start:
...
.
.
.
/* Service routine for IRQ interrupts. */
SERVICE_IRQ:
.
.
.
SUBS
PC, LR, #4 /* Return to interrupted program. */
/* Service routine for software interrupts. */
SERVICE_SVC:
.
.
.
MOVS
PC, LR /* Return to interrupted program. */
Figure 5. Code used to set up the exception processing.
Intel Corporation - FPGA University Program
November 2016
27