I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
MOVT R
d
, #immed16
loads a 16-bit immediate value into the high-order 16 bits of R
d
, and leaves the low-order 16 bits unchanged.
There are also two special instructions, MRS and MSR, which copy the contents of a processor status register to/from
a general-purpose register. These instructions are available only when the processor is running in a privileged mode,
as explained in Section 10.
6.6.1
Loading 32-bit Constants into Registers
The simplest approach is to use the load-register pseudo-instruction
LDR R2,
=
0x12345678
in which case the Assembler will place this constant, and other constants defined in such manner, into a
literal pool
in the memory, from where it will be taken at execution time. In the assembled code, this LDR instruction will use
the Relative addressing mode to access the literal pool. The Assembler decides where in memory to place the literal
pool; typically, it is immediately following the program’s machine code.
A constant may be represented by a name, say LABEL. For example, LABEL may correspond to the address of
some memory location. In that case, this address can be loaded into a register, R
d
, using the pseudo-instruction
LDR
R
d
,
=
LABEL
Again, the Assembler will place the corresponding 32-bit address into the literal pool.
6.7
Shift and Rotate Instructions
ARM has
shift
and
rotate
instruction mnemonics:
• LSL – Logical Shift Left
• LSR – Logical Shift Right
• ASR – Arithmetic Shift Right
• ROR – Rotate Right
An example of a shift instruction is
LSL R2, R5, #4
which shifts the value in R5 to the left by four bit-positions (zeros are inserted on the right) and places the result into
R2. Since
Operand2
of any instruction can be shifted or rotated, it is possible to use Move instructions mnemonics
instead of
shift
and
rotate
. For example, the instruction
Intel Corporation - FPGA University Program
November 2016
13
