Intel ARM Cortex-A9, Introduction Manual

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I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15
User/System Supervisor Abort Undefined IRQ FIQ
CPSR CPSR
CPSR CPSR CPSR CPSR
SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq
SP
LR
PC
Figure 4. Registers used in various operating modes.
Note that registers R0 to R12 are not banked in most operating modes. Thus, when an exception service routine
needs to use some of these registers, the contents of the registers must be saved on the stack and later restored.
However, having the five banked registers R8_fiq to R12_fiq in the FIQ mode, it is possible to respond very quickly
to a fast interrupt request if these registers are sufficient for the task that is implemented by the corresponding
interrupt-service routine.
In Figure 4 and in the above discussion we referred to the specific banked registers by appending a mode specifier,
e.g. R14_svc. In an assembly-language program such specifiers are not included, because the processor accesses the
desired banked register based on its current operating mode, as indicated by the processor-mode bits, CPSR
4
−
0
.
In the Supervisor mode, the special Move instructions, MRS and MSR, can be used to access the processor status
registers CPSR and SPSR_svc. The instruction
MRS R d , CPSR
22 Intel Corporation - FPGA University Program
November 2016