I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
2
Overview of ARM Cortex-A9 Processor Features
The ARM Cortex-A9 processor has mostly a Reduced Instruction Set Computer (RISC) architecture. Its arithmetic
and logic operations are performed on operands in the general-purpose registers. The data is moved between the
memory and these registers by means of
Load
and
Store
instructions.
The word-length of the processor is 32 bits. Data byte addresses in a 32-bit word are assigned in
little-endian
style,
in which the lower byte addresses are used for the less significant bytes (the rightmost bytes) of the word.
3
Register Structure
All registers in the ARM Cortex-A9 processor are 32 bits long. There are 15 general-purpose registers, R0 to R14,
a Program Counter, R15, and a Current Program Status Register, CPSR, as shown in Figure 1. All general-purpose
registers can be used in the same way. However, software programs usually treat two of them in a special way.
Register R13 is used as a Stack Pointer. Register R14 is used as a Link Register in subroutine linkage. In assembly-
language programs, the registers R15, R14 and R13 can also be referred to by using the acronyms PC, LR and SP,
respectively. In assembly-language programs, the register names can be written either in upper or lower case. Thus,
R1, R2, PC, LR and SP is equivalent to r1, r2, pc, lr and sp.
•
•
•
N Z C V
31
29
7
0
28
30
6
4
5
I
F
T
Processor mode
ARM or Thumb operation
Interrupt disable bits
Condition code flags
0
31
R0
R1
R13
R14
R15
SP - Stack pointer
LR - Link register
PC - Program counter
Status register
CPSR
Figure 1. ARM register structure.
2
Intel Corporation - FPGA University Program
November 2016
