I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
6.4
Arithmetic Instructions
As illustrated above, an arithmetic operation such as
ADD R
d
, R
n
,
Operand2
adds the contents of R
n
and the value determined as
Operand2
into R
d
. For example, the instruction
ADD R0, R1, R2, LSL #2
adds the contents of R1 and a shifted version of the contents of R2, and places the sum into R0. The operand R2
is shifted to the left by 2 bit positions (which is equivalent to integer multiplication by 4) before it is used in the
addition.
In an assembly-language instruction, it is possible to specify a negative number as the immediate operand, as in
ADD R0, R1, #
−
24
The Assembler will implement this operation with the Subtract instruction
SUB R0, R1, #24
6.4.1
Multiplication
There are two versions of multiplication instructions:
• MUL – (Multiply)
• MLA – (Multiply Accumulate)
The Multiply instruction
MUL R2, R4, R5
multiplies the contents of registers R4 and R5, and places a 32-bit product into register R2. If the generated product
exceeds 32 bits, then the low-order 32 bits are retained and the high-order bits are discarded.
The MLA instruction multiplies the operands in two registers to produce a 32-bit product, which is then added to
the third operand, and the result is written into the destination register. Thus,
MLA R2, R4, R5, R6
multiplies the numbers in R4 and R5, adds to this product the number in R6, and places the result into register R2.
Intel Corporation - FPGA University Program
November 2016
11
