I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
6.5
Logic and Test Instructions
The logic instructions provide the AND, OR and Exclusive-OR operations. The AND instruction
AND R
d
, R
n
,
Operand2
performs a bitwise logical AND of the contents of register R
n
with the value of
Operand2
, and stores the result in
register R
d
. Similarly, the instructions ORR and EOR perform the OR and Exclusive-OR operations, respectively.
Another useful logic instruction is BIC, which stands for
Bit Clear
. It performs a bitwise AND of the operand in R
n
with the
complement
of
Operand2
, and stores the result in R
d
.
There are two instructions that perform logic operations for testing purposes. The
Test
instruction
TST R
n
,
Operand2
performs the AND operation using the contents of R
n
and
Operand2
, and sets the condition code flags based on the
result obtained. The
Test Equivalence
instruction
TEQ R
n
,
Operand2
compares the value in R
n
with the value represented by
Operand2
. This is done by exclusive-ORing the two values
and setting the condition code flags accordingly.
6.6
Move Instructions
The Move instructions copy the contents of one register into another, or they place an immediate value into a register.
The
Move
instruction
MOV R
d
,
Operand2
moves the value of
Operand2
into register R
d
.
The
Move Negative
instruction
MVN R
d
,
Operand2
moves the complement of the value of
Operand2
into R
d
.
The
Move Top
instruction
12
Intel Corporation - FPGA University Program
November 2016
