I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
ADDS R2, R3, R4
will set the flags, but
ADD R2, R3, R4
will not.
6.10
Conditional Execution of Instructions
Most ARM instructions can be executed conditionally. The high-order four bits in the machine representation of
each instruction, as illustrated in Figure 2, specify a condition that must be met for the instruction to be executed.
These conditions are associated with the condition code flags N, Z, C and V. The instruction is executed only if there
is a match between the specified condition and the current values of the condition code flags.
The general form of data processing instructions is
OP{S}{
cond
}
R
d
, R
n
,
Operand2
The conditions that can be specified are those in Table 2. Observe that there are 14 patterns for conditions that
depend on the condition code flags.
For example, the instruction
ADDEQ R2, R3, R4
will be executed if the condition code flag
Z
is equal to 1. Otherwise, the execution will skip to the next instruction.
The instruction
MOVNE R1, R0
Will transfer the contents of R0 into R1 if the current value of the
Z
flag is 0. If
Z
=
1
, the Move instruction will not
be executed and the processor will skip to the next instruction.
6.11
Branch Instructions
The flow of execution of a program can be changed by executing a
Branch
instruction. It may be changed either
conditionally or unconditionally.
A branch instruction is specified as
Intel Corporation - FPGA University Program
November 2016
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