I
NTRODUCTION TO THE
ARM
®
P
ROCESSOR
U
SING
I
NTEL
FPGA T
OOLCHAIN
For Quartus Prime 16.1
MOV R2, R5, LSL #4
is equivalent to the LSL instruction shown above. Also, the same effect can be achieved with the instruction
LSL R2, R5, R6
if the contents of R6 are equal to 4. There is also a logical shift right, LSR, instruction, in which bits are shifted to
the right with zeros being inserted on the left. Similarly, arithmetic shift right, ASR, performs a shift to the right, but
in this case the
sign
bit,
b
31
, is replicated on the left for each shift position. Another example is
ROR R3, R3, #8
which rotates the contents of R3 to the right by eight bit-positions. In the
rotate
instruction bits shifted out of position
b
0
on the right are inserted into position
b
31
on the left, in a circular fashion.
6.8
Comparison Instructions
The comparison instructions compare the contents of two registers or the contents of a register and an immediate
value, and set the condition code flags based on the result.
The Compare instruction
CMP R
n
,
Operand2
performs the comparison by subtracting the value of
Operand2
from the value in R
n
. It sets the condition code flags,
but it does not change the contents of R
n
.
The
Compare Negative
instruction
CMN R
n
,
Operand2
performs the comparison by adding the value of
Operand2
and the value in R
n
. It sets the condition code flags, but
it does not change the contents of R
n
.
6.9
Setting of Condition Code Flags
The condition code flags are always affected by the compare instructions, CMP and CMN, and the test instructions,
TST and TEQ. Many other instructions can also affect the condition code flags, but this must be specified in the
instruction. The data processing instructions (arithmetic, logic and move) affect these flags if the suffix
S
is appended
to the assembly-language OP-code mnemonic, as we mentioned in Section
6.3.1
.
For example, the instruction
14
Intel Corporation - FPGA University Program
November 2016
