Intel ARCHITECTURE IA-32, Reference Manual

Page: 49 / 568

IA-32 Intel® Architecture Processor Family Overview
1-21
back within the processor, and 6-12 bus cycles to access memory if
there is no bus congestion. Each bus cycle equals several processor
cycles. The ratio of processor clock speed to the scalable bus clock
speed is referred to as bus ratio. For example, one bus cycle for a
100 MHz bus is equal to 15 processor cycles on a 1.50 GHz processor.
Since the speed of the bus is implementation-dependent, consult the
specifications of a given system for further details.
Data Prefetch
The Pentium 4 processor and other IA-32 processors based on the
NetBurst microarchitecture have two type of mechanisms for
prefetching data: software prefetch instructions and hardware-based
prefetch mechanisms.
Software controlled prefetch is enabled using the four prefetch
instructions (PREFETCHh) introduced with SSE. The software prefetch
is not intended for prefetching code. Using it can incur significant
penalties on a multiprocessor system if code is shared.
Software prefetch can provide benefits in selected situations. These
situations include:
•
when the pattern of memory access operations in software allows
the programmer to hide memory latency
•
when a reasonable choice can be made about how many cache lines
to fetch ahead of the line being execute
•
when an choice can be made about the type of prefetch to use
SSE prefetch instructions have different behaviors, depending on cache
levels updated and the processor implementation. For instance, a
processor may implement the non-temporal prefetch by returning data
to the cache level closest to the processor core. This approach has the
following effect:
•
minimizes disturbance of temporal data in other cache levels