Intel ARCHITECTURE IA-32, Reference Manual

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Multi-Core and Hyper-Threading Technology
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7-43
Preventing Excessive Evictions in First-Level Data Cache
Cached data in a first-level data cache are indexed to linear addresses
but physically tagged. Data in second-level and third-level caches are
tagged and indexed to physical addresses. While two logical processors
in the same physical processor package execute in separate linear
address space, the same processors can reference data at the same linear
address in two address spaces but mapped to different physical
addresses. When such competing accesses occur simultaneously, they
can cause repeated evictions and allocations of cache lines in the
first-level data cache. Preventing unnecessary evictions in the first-level
data cache by two competing threads improves the temporal locality of
the first-level data cache.
Multithreaded applications need to prevent unnecessary evictions in the
first-level data cache when:
•
Multiple threads within an application try to access private data on
their stack, some data access patterns can cause excessive evictions
of cache lines. Within the same software process, multiple threads
have their respective stacks, and these stacks are located at different
linear addresses. Frequently the linear addresses of these stacks are
spaced apart by some fixed distance that increases the likelihood of
a cache line being used by multiple threads.
•
Two instances of the same application run concurrently and are
executing in lock steps (for example, corresponding data in each
instance are accessed more or less synchronously), accessing data
on the stack (and sometimes accessing data on the heap) by these
two processes can also cause excessive evictions of cache lines
because of address conflicts.