Intel ARCHITECTURE IA-32, Reference Manual

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Using Performance Monitoring Events
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that logical processor is not halted (it may include some portion of the
clock cycles for that logical processor to complete a transition into a
halted state). A physical processor that supports Hyper-Threading
Technology enters into a power-saving state if all logical processors are
halted.
“Non-sleep clockticks” use is based on the filtering mechanism in the
CCCR: it will continue to increment as long as one logical processor is
not halted, nor is it in any power-saving states. An application may
indirectly cause a processor to enter into a power-saving state via an OS
service that transfers control into the operating system's idle loop. The
system idle loop may place the processor into a power-saving state after
an implementation-dependent period if there is no work for the
processor to do.
Time Stamp Counter
The time stamp counter increments whenever the sleep pin is not
asserted or when the clock signal on the system bus is active. It can be
read with the RDTSC instruction. The difference in values between two
reads (modulo 2**64) gives the number of processor clocks between
those reads.
The time stamp counter and “Non-sleep clockticks” counts should agree
in practically all cases if the physical processor is not in any
power-saving states. However, it is possible to have both logical
processors in a physical package halted, which results in most of the
chip (including the performance monitoring hardware) being powered
down. In this situation, it is possible for the time stamp counter to
continue incrementing because the clock signal on the system bus is still
active, but “non-sleep clockticks” will no longer increment because the
performance monitoring hardware is powered down in power-saving
states.