IA-32 Intel® Architecture Optimization
2-74
Complex Instructions
Assembly/Compiler Coding Rule 40. (ML impact, M generality) Avoid
using complex instructions (for example,
enter
,
leave
, or
loop
) that have
more than four µops and require multiple cycles to decode. Use sequences of
simple instructions instead.
Complex instructions may save architectural registers, but incur a
penalty of 4 µops to set up parameters for the microcode ROM.
Use of the
lea
Instruction
In many cases, the
lea
instruction or a sequence of
lea
,
add
,
sub
and
shift
instructions can replace constant multiply instructions. The
lea
instruction can also be used as a multiple operand addition instruction,
for example:
lea ecx, [eax + ebx + 4 + a]
Using
lea
in this way may avoid register usage by not tying up registers
for operands of arithmetic instructions. This use may also save code
space.
If the
lea
instruction uses a shift by a constant amount then the latency
of the sequence of µops is shorter if
add
s are used instead of a shift, and
the
lea
instruction may be replaced with an appropriate sequence of
µops. This, however, this increases the total number of µops, leading to
a trade-off.
Assembly/Compiler Coding Rule 41. (ML impact, M generality) If a
lea
instruction using the scaled index is on the critical path, a sequence with
add
s
may be better. If code density and bandwidth out of the trace cache are the
critical factor, then use the
lea
instruction.
Summary of Contents for ARCHITECTURE IA-32
Page 1: ...IA 32 Intel Architecture Optimization Reference Manual Order Number 248966 013US April 2006...
Page 220: ...IA 32 Intel Architecture Optimization 3 40...
Page 434: ...IA 32 Intel Architecture Optimization 9 20...
Page 514: ...IA 32 Intel Architecture Optimization B 60...
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