Infineon OPTIREG TLF30681QVS01, Manual

Page: 85 / 133

9 SPI registers
Table 28 Abbreviations
R0 Register is reset on a POR event and on a transition into DISABLED state.
R1 Register is reset with reset class R0 and additionally on a transition into LOCKED state.
R2 Register is reset with reset class R1 and additionally on a microcontroller reset.
r Bit is readable (read-only).
rw Bit is readable and writable (read-write).
rw1p Bit is protected. Read data is inverted. Write via LOCK/UNLOCK mechanism only.
rw1c Bit is readable and can be cleared by a write operation with 1.
Bit is updated based on hardware inputs (flags).
rwhc Bit is readable and writable. After a write operation with 1 an operation is triggered which
upon its completion sets the bit to 0.
rwhu Bit is readable and writable.
Bit is updated based on hardware inputs (flags).
Table 29 Register overview
Register ID Description Address Reset
Value
Reset
Class
Page
DEVCFG0 Device configuration 0 00
H
F3
H
R0 Page 88
CLKCFG0 Clock configuration 0 01
H
00
H
R2 Page 89
CLKCFG1 Clock configuration 1 02
H
04
H
R2 Page 90
PROTCFG Configuration protection 03
H
00
H
R2 Page 102
PWDCFG0 Protected watchdog configuration 0 06
H
9B
H
R2 Page 91
RWDCFG0 Read-only watchdog configuration 0 07
H
9B
H
R2 Page 94
PWDCFG1 Protected watchdog configuration 1 08
H
46
H
R2 Page 92
RWDCFG1 Read-only watchdog configuration 1 09
H
46
H
R2 Page 95
PWDCFG2 Protected Watchdog Configuration 2 0A
H
78
H
R2 Page 93
RWDCFG2 Read-only watchdog configuration 2 0B
H
78
H
R2 Page 96
B2VCTRL Buck2 output voltage control 10
H
02
H
R1 Page 100
B2VCTRLN Buck2 output voltage control inverted 11
H
0D
H
R1 Page 101
GSF Global status flags 1A
H
00
H
R0 Page 104
SYSSF0-QM System status flags – faults 1B
H
00
H
R0 Page 106
SYSSF1-QM System status flags – interrupts 1C
H
00
H
R1 Page 107
MCUSF0-QM Microcontroller status flags 0 – faults 1D
H
00
H
R0 Page 109
MCUSF1-QM Microcontroller status flags 1 – warnings 1E
H
00
H
R1 Page 110
SPISF SPI status flags 1F
H
00
H
R1 Page 111
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
SPI registers
Datasheet 85 Rev. 1.0
2020-04-08