9.1.5
Event status registers
The event status registers of the device are organized hierarchically. The global status register is used to collect
information of the status flags set in other registers to enable the user to speed up the event source
determination.
A bit in the global status register is automatically set, when a bit in the respective status register is set (event
based, not level based).
If a bit in the global status register is set, the user should read out the corresponding status register for the
detailed information on the event source.
The bits in the global status flag register can be cleared without effect on the other status registers. Clearing a
bit in any of the other status registers does not reset the corresponding bit in the global status register.
9.1.5.1
Register GSF
GSF
RMAP: X
Address:
1A
H
Global status flags
PAGE: 0
Reset Value:
00
H
7
6
5
4
3
2
1
0
INTMISS
nu
R1VSxUV
OT
MON
SPI
MCU
SYS
r
r
rw1c
rw1c
rw1c
rw1c
rw1c
rw1c
Field
Bits
Type
Description
INTMISS
7
r
Interrupt timeout event
0
H
, no event
1
H
, event occurred, cleared by hardware when all other flags in
IF are cleared.
Reset: 0
H
nu
6
r
Not used
R1VSxUV
5
rw1c
Battery voltage undervoltage event
0
H
, no event, write 0 – no action
1
H
, event occurred, write 1 to clear the flag
Reset: 0
H
OT
4
rw1c
Overtemperature or overcurrent monitoring event flag:
0
H
, no event, write 0 – no action
1
H
, event occurred, write 1 to clear the flag
Reset: 0
H
MON
3
rw1c
Voltage monitoring event flag:
,
0
H
, no event, write 0 – no action
1
H
, event occurred, write 1 to clear the flag
Reset: 0
H
SPI
2
rw1c
SPI event flag:
0
H
, no event, write 0 – no action
1
H
, event occurred, write 1 to clear the flag
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
SPI registers
Datasheet
104
Rev. 1.0
2020-04-08
