Document Number: 001-98285 Rev. *R
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
1.
Product Overview
The GL-S family consists of 128-Mbit to 1Gbit, 3.0 V core, Versatile I/O, non-volatile, flash memory devices. These devices have a
16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits of data on each bus transfer
cycle. All writes take 16 bits of data from each bus transfer cycle.
Figure 1.1
Block Diagram
:
Note:
** A
MAX
GL01GS = A25, A
MAX
GL512S = A24, A
MAX
GL256S = A23, A
MAX
GL128S = A22
The GL-S family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast
random access of XIP flash along with the high density and fast program speed of Data Storage flash.
Read access to any random location takes 90 ns to 120
ns depending on device density and I/O power supply voltage. Each random
(initial) access reads an entire 32-byte aligned group of data called a Page. Other words within the same Page may be read by
changing only the low order 4 bits of word address. Each access within the same Page takes 15 ns to 30 ns. This is called Page
Mode read. Changing any of the higher word address bits will select a different Page and begin a new initial access. All read
accesses are asynchronous.
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
V
IO
WE#
WP#
CE#
OE#
STB
STB
DQ15
–
DQ0
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A
Max
**–A0
