Infineon Cypress S29GL01GS, Manual

Page: 37 / 109

Document Number: 001-98285 Rev. *R Page 36 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Figure 5.5 Data# Polling Algorithm
Note:
1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
5.5.2.2 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Program Suspend or Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior to the program or erase operation).
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if the sector selected for erasing is protected, DQ6 toggles for approximately 100 µs,
then the EAC returns to standby (Read Mode). If the selected sector is not protected, the Embedded Erase algorithm erases the
unprotected sector.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or erase-suspended. When the device
is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Program
Suspend mode or Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors
are erasing, or erase-suspended. Alternatively, the system can use DQ7 (see
DQ7: Data# Polling on page 35 ).
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Table 5.3 on page 39 shows the outputs for Toggle Bit I on DQ6. Figure 5.6 on page 37 shows the toggle bit algorithm in flowchart
form, and the Reading Toggle Bits DQ6/DQ2 on page 37 explains the algorithm. Figure 5.6 on page 37 shows the toggle bit timing
diagrams. Figure 5.2 on page 25 shows the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II
on page 37 .
5.5.2.3 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. See
Sector Erase on page 29 for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure
that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun;
all further commands (except Erase Suspend) are ignored until the erase operation is complete.
Table 5.3 on page 39 shows the
status of DQ3 relative to the other status bits.
START
Read DQ7 -DQ0 -
FAIL
DQ7 = Data?
No
Yes
DQ5 = 1?
No
Yes
DQ7 = Data?
No
Yes
PASS
Read DQ 7 -DQ0