Document Number: 001-98285 Rev. *R
Page 87 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Note:
1. If this timing cannot be achieved, perform the following steps immediately after ASO Exit and before resuming normal processing: read one word from each of 64
unique 32 byte-aligned pages.
Figure 11.16
ASO Entry Timing
Note:
1. Applicable to any ASO entry command.
Figure 11.17
Data# Polling Timing Diagram (During Embedded Algorithms)
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Table 11.9
ASO Entry Timing
t
ASOSTART
Falling edge of CE# or address change whichever comes last
t
ASOEND
Rising edge of CE# or Rising edge of WE# whichever comes first
t
ASOENTRY
25 ns < t
ASOENTRY
< 50 ns or t
ASOENTRY
> 150 ns
CE#
WE#
Addresses
First command cycle to enter ASO
t
ASOSTART
t
ASOEND
t
ASOENTRY
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6–DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Valid Data
Valid Data
t
ACC
t
RC
Status Data
True
