Infineon Cypress S29GL01GS Manual Download | Manualshive

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Document Number: 001-98285 Rev. *R

Page 90 of 108

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

12. Physical Interface

12.1

56-pin TSOP

12.1.1

Connection Diagram

Figure 12.1

56-pin Standard TSOP

Notes:
1. Pin 28, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Cypress for test or other purposes and is

not intended for connection to any host system signal. Do not use these connections for PCB Signal routing channels. Though not recommended, the ball can be
connected to V

CC

or V

SS

through a series resistor.

2. Pin 27, 30, and 53 Reserved for Future Use (RFU).

3

18

4

1
2

5
6
7
8
9
10

19
20
21
22
23
24

11
12
13
14
15
16
17

46
45

48
47

44
43
42

40

41

54
53

55

56

52
51
50
49

39
38
37
36
35
34
33
32
31
30

56-Pin TSOP

25
26
27
28

29

A15

A18

A14
A13
A12
A11
A10

A9
A8

A19
A20

WE#

RESET#

A21

WP#

RY/BY#

A17

A7
A6
A5

A23
A22

A4
A3
A2
A1

RFU

DNU

A24
A25

DQ10

A16
RFU
V

SS

DQ15
DQ7
DQ14
DQ6

DQ2

DQ9
DQ1
DQ8

DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3

DQ0
OE#

V

SS

CE#
A0

V

IO

RFU

NC for GL256S, GL128S
NC for GL512S, GL256S, GL128S

NC for GL128S

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Summary of Contents for Cypress S29GL01GS

Page 1: ...rs as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes t...

Page 2: ...ology Single supply VCC for read program erase 2 7 V to 3 6 V Versatile I O Feature Wide I O voltage range VIO 1 65 V to VCC 16 data bus Asynchronous 32 byte Page read 512 byte Programming Buffer Prog...

Page 3: ...ull VCC VIO 90 15 90 25 VersatileIO VIO 100 25 100 35 256 Mb Full VCC VIO 90 15 90 25 VersatileIO VIO 100 25 100 35 512 Mb Full VCC VIO 100 15 100 25 VersatileIO VIO 110 25 110 35 1 Gb Full VCC VIO 10...

Page 4: ...6 2 Data Retention 54 7 Software Interface Reference 55 7 1 Command Summary 55 7 2 Device ID and Common Flash Interface ID CFI ASO Map 58 7 3 Device ID and Common Flash Interface ID CFI ASO Map 63 8...

Page 5: ...the high density and fast program speed of Data Storage flash Read access to any random location takes 90 ns to 120 ns depending on device density and I O power supply voltage Each random initial acc...

Page 6: ...g is done via a 512 byte Write Buffer It is possible to write from 1 to 256 words anywhere within the Write Buffer before starting a programming operation Within the flash memory array each 512 byte a...

Page 7: ...The main Flash Memory Array is the primary and default address space but it may be overlaid by one other address space at any one time Each alternate address space is called an Address Space Overlay A...

Page 8: ...programmed to change 1 s to 0 s Secure Silicon Region Lock Register Persistent Protection Bits PPB Password Only the PPB ASO has non volatile data that may be erased to change 0 s to 1 s When a progra...

Page 9: ...fferent devices but adjusts the driver behavior based on the information in the CFI table Traditionally these two address spaces have used separate commands and were separate overlays However the mapp...

Page 10: ...ies of devices The data structure contains information for system configuration such as various electrical and timing parameters and special functions supported by the device Software support can then...

Page 11: ...data polling is not supported for these commands The Data Polling Status word appears at all word locations in the device address space When an EA is completed the Data Polling Status ASO is exited a...

Page 12: ...ts However it is recommended to read or program the PPB Lock only at address 0 of the device for future compatibility 2 7 4 Password ASO The Password ASO contains four words of OTP memory When the ASO...

Page 13: ...U RFU RFU RFU RFU RFU RFU Value X X X X X X X X Table 2 8 ECC Status Word Lower Byte Bit 7 6 5 4 3 2 1 0 Name RFU RFU RFU RFU RFU Single Bit Error corrected in the 8 bit error correction code Single B...

Page 14: ...C examines the address and data in each write transfer to determine if the write is part of a legal command sequence When a legal command sequence is complete the EAC will initiate the appropriate EA...

Page 15: ...volatile DYB protection bit associated with it When either bit is 0 the sector is protected from program and erase operations The PPB bits are protected from program and erase when the PPB Lock bit is...

Page 16: ...the PPBs are configured to the desired settings In Persistent Protection mode the PPB Lock is set to 1 during POR or a hardware reset When cleared no software command sequence can set the PPB Lock onl...

Page 17: ...as once locked there is no procedure available for unlocking the protected portion of the Secure Silicon Region and none of the bits in the protected Secure Silicon Region memory space can be modifie...

Page 18: ...ersistent Protection method sets the PPB Lock to 1 during POR or Hardware Reset so that the PPB bits are unprotected by a device reset There is a command to clear the PPB Lock bit to 0 to protect the...

Page 19: ...hey don t match to the internal set value than the status register will return to the ready state with the Program Status Bit set to 1 and Program Status Register Bit set to 1 indicating a failed prog...

Page 20: ...eads within the same Page have faster read access speed The Page is selected by the higher address bits AMAX A4 while the specific word of that page is selected by the least significant address bits A...

Page 21: ...address and data sequences command sequences switch the memory device address space from the main flash array to one of the Address Space Overlays ASO Embedded Algorithms operate on the information v...

Page 22: ...of a program or erase operation by reading the Status Register or using Data Polling Status Refer to Status Register on page 34 for information on these status bits Refer to Data Polling Status on pa...

Page 23: ...error found in a Page during a read access The first Write Buffer program operation applied to a Page programs the ECC Code for that Page Subsequent programming operations that occur more than once on...

Page 24: ...Y output See Status Register on page 34 for information on these status bits See Data Polling Status on page 35 for information on these status bits See Figure 5 1 on page 23 for a diagram of the prog...

Page 25: ...ble during the write buffer loading period The only way to stop loading the write buffer is to write with an address that is outside the Line of the programming operation This invalid address will imm...

Page 26: ...on page 55 for the command sequence as required for Write Buffer Programming 4 When Sector Address is specified any address in the selected sector is acceptable However when loading Write Buffer addre...

Page 27: ...cted Write Buffer Page Write Write to Buffer command Sector Address Write Word Count to program 1 WC Sector Address Write Starting Address Data WC 0 ABORT Write to Buffer Operation Write to a differen...

Page 28: ...a programming operation while an erase is suspended In this case data may be read from any addresses not in Erase Suspend or Program Suspend After the Program Resume command is written the device rev...

Page 29: ...tire main Flash Memory Array The device does not require the system to preprogram prior to erase The Embedded Erase algorithm automatically programs and verifies the entire memory for an all 0 data pa...

Page 30: ...Data Polling Status on page 35 for more information Once the sector erase operation has begun the Status Register Read and Erase Suspend commands are valid All other commands are ignored However note...

Page 31: ...n on these status bits Refer to Data Polling Status on page 35 for more information After an erase suspended program operation is complete the EAC returns to the erase suspend state The system can det...

Page 32: ...efer to the Cypress Low Level Driver User s Guide available on www cypress com for general information on Cypress flash memory software development guidelines Example CFI Entry command UINT16 base_add...

Page 33: ...th the Password Unlock command ASO Exit using legacy Command Set Exit command for backward software compatibility ASO Exit using the common exit command for all ASO alternative for a consistent exit m...

Page 34: ...sed for the following conditions Exit ID CFI mode Clear timeout bit DQ5 for data polling when timeout occurs Software Reset does not affect EA mode Reset commands are ignored once programming or erasu...

Page 35: ...rrent state bits indicate whether an EA is in process suspended or completed The upper 8 bits bits 15 8 are reserved These have undefined High or Low value that can change from one status read to anot...

Page 36: ...Buffer Programming Reading Data Polling status on any word other than the last word to be programmed in the write buffer page will return false status information During the Embedded Program algorith...

Page 37: ...ss DQ6 toggles When the device enters the Program Suspend mode or Erase Suspend mode DQ6 stops toggling However the system must also use DQ2 to determine which sectors are erasing or erase suspended A...

Page 38: ...second read the system would compare the new value of the toggle bit with the previous value If the toggle bit is not toggling the device has completed the program or erases operation The system can r...

Page 39: ...roduces a 1 This is a failure condition that indicates the program or erase cycle was not successfully completed The system must issue the reset command to return the device to reading array data When...

Page 40: ...lid data 4 DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations 5 Applies only to program operations Table 5 3 Data Polling Status Operation DQ7 Note 2 DQ6 DQ5 Not...

Page 41: ...status the Data Polling status will show the following DQ7 is the inversion of the DQ7 bit in the last word loaded into the write buffer or last word of the password in the case of the password unlock...

Page 42: ...reated as don t care masked DQ3 1 to indicate embedded sector erase in progress DQ2 continues to toggle independent of the address used to read status DQ1 0 Write buffer abort error DQ0 is RFU and sho...

Page 43: ...n t care and should be masked DQ2 does not toggle after program operation as no erase is in progress If the Write Buffer Program operation was started after an erase operation had been suspended then...

Page 44: ...Table 5 4 Embedded Algorithm Characteristics 40 C to 85 C Parameter Typ Note 2 Max Note 3 Unit Comments Sector Erase Time 128 kbyte 275 1100 ms Includes pre programming prior to erasure Note 5 Single...

Page 45: ...Characteristics 40 C to 105 C Parameter Typ Note 2 Max Note 3 Unit Comments Sector Erase Time 128 kbyte 275 1100 ms Includes pre programming prior to erasure Note 5 Single Word Programming Time Note...

Page 46: ...ID Auto select Entry SSR Entry Lock Register Entry Password ASO Entry PPB Entry PPB Lock Entry DYB ASO Entry Address RA x555h x2AAh x555h SA xh x555h SA 555 h SA 555 h x555h x555h x555h x555h x555h Da...

Page 47: ...nlock 1 Word Progra m Entry Write to Buffer Enter Write to Buffer Abort Reset Start Erase Resume Enhance d Method 1 DYB ASO Entry NOT a valid Write to Buffer Abort Reset Command Address RA xh x555h x2...

Page 48: ...PG ESPG SR 7 0 ESPG ESPGSR ESPG ESPSR ESPG ESPSR ESPG ESPG SR 7 1 ES ES ESUL1 ESPGSR return return Table 5 13 Erase Suspend Program Suspend Command State Transition Current State Command and Condition...

Page 49: ...ftware Reset ASO Exit Status Register Read Enter Unlock 2 NOT a valid Write to Buffer Abort Reset Command Address RA xh x555h x2AAh NOT x555h xh NOT x2AAh xh Data RD xF0h x70h x55h xh NOT xF0h xh NOT...

Page 50: ...55h x555h Data RD xF0h x70h x71h CFI CFI READ CFISR CFI CFI CFISR return Table 5 19 Secure Silicon Sector State Command Transition Current State Command and Condition Read Software Reset ASO Exit Stat...

Page 51: ...Write Buffer Write Buffer SSRPG SR 7 0 SSRPG SSRSR SSRPG SR 7 1 SSR SR 7 1 and DQ 1 0 READ DQ 1 1 SSRUL1 SR 3 1 SSRSR return SSREXT SSREXT SSRSR SSR READ Table 5 22 Password Protection Command State T...

Page 52: ...D Table 5 24 PPB Lock Bit Command State Transition Current State Command and Condition Read Software Reset ASO Exit Status Register Read Enter Status Register Clear Command Set Exit Entry Command Set...

Page 53: ...ble 5 12 Erase Suspended Program Status Register Read ESPG1 Table 5 12 Erase Suspended Word Program ESPS Table 5 13 Erase Suspended Program Suspended ESPSR Table 5 13 Erase Suspended Program Suspend E...

Page 54: ...st PSSR Table 5 16 Program Suspended Status Register Read PPWB25 Table 5 22 Password ASO Unlock READ Table 5 6 Read Array READSR Table 5 6 Read Status Register READUL1 Table 5 7 Read Unlock Cycle 1 RE...

Page 55: ...ata Retention Contact Cypress Sales or an FAE representative for additional information on the data integrity An application note is available at http www cypress com appnotes Table 6 1 Erase Enduranc...

Page 56: ...555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend Program Suspend Legacy Method Note 9 1 XXX B0 Erase Suspend Enhanced Method Erase Resume Program Resume Legacy Method Note...

Page 57: ...Exit Notes 7 16 1 XXX F0 Non Volatile Sector Protection Command Set Definitions PPB Non Volatile Sector Protection PPB Entry 3 555 AA 2AA 55 555 C0 PPB Program Note 17 2 XXX A0 SA 0 All PPB Erase Note...

Page 58: ...valid only during the Erase Suspend Program Suspend modes 11 Issue this command sequence to return to READ mode after detecting device is in a Write to Buffer Abort state IMPORTANT the full command s...

Page 59: ...is not supported Page mode read between ID locations other than 02h is supported For additional information see ID CFI ASO on page 31 Table 7 2 ID Autoselect Address Map Description Address Read Data...

Page 60: ...are Bits SA 000Dh Reserved Device ID SA 000Eh 2228h 1 Gb 2223h 512 Mb 2222h 256 Mb 2221h 128 Mb Device ID SA 000Fh 2201h Table 7 3 CFI Query Identification String Word Address Data Description SA 0010...

Page 61: ...for buffer write 2N times typical SA 0025h 0003h Max timeout per individual block erase 2N times typical SA 0026h 0003h Max timeout for full chip erase 2N times typical 00h not supported Table 7 5 CFI...

Page 62: ...SA 0043h 0031h Major version number ASCII SA 0044h 0035h Minor version number ASCII SA 0045h 001Ch Address Sensitive Unlock Bits 1 0 00b Required 01b Not Required Process Technology Bits 5 2 0000b 0...

Page 63: ...ot 02h Bottom Boot Device with WP Protect Bottom Boot 03h Top Boot Device with WP Protect Top Boot 04h Uniform Bottom WP Protect Uniform Bottom Boot 05h Uniform Top WP Protect Uniform Top Boot 06h WP...

Page 64: ...terface ID CFI ASO Map Word Address Data Field of bytes Data Format Example of Actual Data Hex Read Out of Example Data SA 0080h Size of Electronic Marking 1 Hex 19 0013h SA 0081h Revision of Electron...

Page 65: ...dress 64 kword 128 kB sector of the device At VIH the sector is not protected WP has an internal pull up When unconnected WP is at VIH RY BY Output open drain Ready Busy Indicates whether an Embedded...

Page 66: ...ogramming or resetting This includes programming in the Erase Suspend mode If the output is High Ready the device is ready to read data including during the Erase Suspend mode or is in the standby mod...

Page 67: ...d off when the core power supply VCC drops below the lock out voltage VLKO When VCC is below VLKO the entire memory array is protected against a program or erase operation This ensures that no spuriou...

Page 68: ...standby level current achieved 9 4 Read 9 4 1 Read With Output Disable When the CE signal is asserted Low the host system memory controller begins a read or write data transfer Often there is a period...

Page 69: ...a WE controlled Write When WE is High and CE goes High there is a transition to the Standby state If CE remains Low and WE goes High there is a transition to the Read with Output Disable state When WE...

Page 70: ...ove those indicated in the operational sections of this data sheet is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability 10 2 L...

Page 71: ...art will stay initialized and will work correctly when VCC is again above VCC minimum If the part locks up from improper initialization a hardware reset can be used to initialize the part correctly No...

Page 72: ...10 4 4 Input Signal Overshoot Figure 10 3 Maximum Negative Overshoot Waveform Figure 10 4 Maximum Positive Overshoot Waveform VCC max VCC min VCC and VIO time VRST min tPD tVCS No Device Access Allow...

Page 73: ...ded pull up resistor for RY BY output is 5k to 10k Ohms Table 10 4 DC Characteristics 40 C to 85 C Parameter Description Test Conditions Min Typ Note 2 Max Unit ILI Input Load Current VIN VSS to VCC V...

Page 74: ...up resistor for RY BY output is 5k to 10k Ohms Table 10 5 DC Characteristics 40 C to 105 C Parameter Description Test Conditions Min Typ Note 2 Max Unit ILI Input Load Current VIN VSS to VCC VCC VCC m...

Page 75: ...8 9 pF COUT Output Capacitance VOUT 0 5 7 pF CIN2 Control Pin Capacitance VIN 0 4 8 pF RY BY Output Capacitance VOUT 0 3 4 pF Table 10 7 Connector Capacitance for FBGA LAE Package Parameter Symbol Pa...

Page 76: ...Outputs Steady Changing from H to L Changing from L to H Don t Care Any Change Permitted Changing State Unknown Does Not Apply Center Line is High Impedance State High Z Table 11 1 Test Specification...

Page 77: ...algorithms and default state from non volatile memory During the Cold Reset period all control signals including CE and RESET are ignored If CE is Low during tVCS the device may draw higher than norm...

Page 78: ...dded Algorithm is stopped and the EAC is returned to its POR state without reloading EAC algorithms from non volatile memory After the Warm Reset EA completes the interface will remain in the Hardware...

Page 79: ...urs First Min 0 ns tEHQZ tDF Chip Enable or Output Enable to Output High Z Note 1 Max 15 ns tOEH Output Enable Hold Time Note 1 Read Min 0 ns Toggle and Data Polling Min 10 ns tASSB Automatic Sleep to...

Page 80: ...Gb 15 20 tGLQV tOE Output Enable to Output Delay Max 25 ns tAXQX tOH Output Hold time from addresses CE or OE Whichever Occurs First Min 0 ns tEHQZ tDF Chip Enable or Output Enable to Output High Z N...

Page 81: ...Output Enable to Output Delay Max 35 ns tAXQX tOH Output Hold time from addresses CE or OE Whichever Occurs First Min 0 ns tEHQZ tDF Chip Enable or Output Enable to Output High Z Note 1 Max 20 ns tOE...

Page 82: ...Number 001 98285 Rev R Page 81 of 108 S29GL01GS S29GL512S S29GL256S S29GL128S Figure 11 7 Page Read Timing Diagram Note Word Configuration Toggle A0 A1 A2 and A3 Amax A4 A3 A0 CE OE DQ15 DQ0 tACC tOE...

Page 83: ...ime to OE Low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE or OE High during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 30 ns...

Page 84: ...29GL128S Figure 11 9 Back to Back CE VIL Write Operation Timing Diagram Figure 11 10 Write to Read tACC Operation Timing Diagram Amax A0 CE OE WE DQ15 DQ0 tDS tDH tWP tAS tAH tWPH tWC tCS Amax A0 CE O...

Page 85: ...ure 11 11 Write to Read tCE Operation Timing Diagram Figure 11 12 Read to Write CE VIL Operation Timing Diagram Amax A0 CE OE WE DQ15 DQ0 tACC tOE tOEH tCE tDF tDF tOH tOH tOH tAS tAH tDS tDH tWP tCS...

Page 86: ...V to VCC VIO 1 65 V to VCC Unit JEDEC Std tWHWH1 tWHWH1 Write Buffer Program Operation Typ Note 3 s Effective Write Buffer Program Operation per Word Typ Note 3 s Program Operation per Word or Page Ty...

Page 87: ...address for sector erase VA valid address for reading status data OE WE CE Data Addresses tDS tAH tDH tWP PD tWHWH1 tWC tAS tWPH 555h PA PA Read Status Data last two cycles A0h tCS Status DOUT Program...

Page 88: ...orithms Note 1 VA Valid address Illustration shows first status cycle after command sequence last status read cycle and array data read cycle Table 11 9 ASO Entry Timing tASOSTART Falling edge of CE o...

Page 89: ...V to VCC Unit JEDEC Std tAVAV tWC Write Cycle Time Note 1 Min 60 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE Low during toggle bit polling Min 15 ns tWLAX tAH Address Hold T...

Page 90: ...fore Write OE High to WE Low Min 0 ns tWLEL tWS WE Setup Time Min 0 ns tELWH tWH WE Hold Time Min 0 ns tELEH tCP CE Pulse Width Min 25 ns tEHEL tCPH CE Pulse Width High Min 20 ns Table 11 10 Alternate...

Page 91: ...ions for PCB Signal routing channels Though not recommended the ball can be connected to VCC or VSS through a series resistor 2 Pin 27 30 and 53 Reserved for Future Use RFU 3 18 4 1 2 5 6 7 8 9 10 19...

Page 92: ...LOWABLE MOLD PROTUSION IS 0 15 mm PER SIDE 5 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0 08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION MINIMUM...

Page 93: ...ot use these connections for PCB Signal routing channels Though not recommended the ball can be connected to VCC or VSS through a series resistor 2 Balls F7 and G1 Reserved for Future Use RFU 3 Balls...

Page 94: ...LLS 3623 16 038 12 1 16 07 NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT AS NOTED 4 e REPRESENT...

Page 95: ...DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 ALL DIMENSIONS ARE IN MILLIMETERS 3 BALL POSITION DESIGNATION PER JESD 95 1 SPP 010 EXCEPT AS NOTED 4 e REPRESENTS THE SOLDER BALL GRID PITCH 5 SYM...

Page 96: ...stem signal Do not use these connections for PCB Signal routing channels Though not recommended the ball can be connected to VCC or VSS through a series resistor 2 Balls E7 F8 and H5 Reserved for Futu...

Page 97: ...IRECTION SYMBOL ME IS THE BALL MATRIX SIZE IN THE E DIRECTION N IS THE TOTAL NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME 6 DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER IN...

Page 98: ...1 01 02 S29GL01GS11DHVyyx S29GL01GS11TFVyyx DHI FHI TFI Note 1 V1 V2 S29GL01GS11DHIyyx S29GL01GS11FHIyyx S29GL01GS11TFIyyx 120 DHV TFV Note 1 V1 V2 S29GL01GS12DHVyyxx S29GL01GS12TFVyyxx S29GL512S 100...

Page 99: ...DHIyyx S29GL128S90FAIyyx S29GL128S90FHIyyx S29GL128S90GHIyyx S29GL128S90TFIyyx 100 DHV TFV Note 1 01 02 S29GL128S10DHVyyx S29GL128S10TFVyyx DHI FAI FHI TFI Note 1 V1 V2 S29GL128S10DHIyyx S29GL128S10FA...

Page 100: ...require ISO TS 16949 compliance Notes 1 Additional speed package and temperature options maybe offered in the future Check with your local sales representative for availability 2 Package Type 0 is st...

Page 101: ...Model Number x Packing Type S29GL01GS 110 DHB FHB TFB GHB Note 1 01 02 0 3 Note 2 S29GL01GS11DHByyx S29GL01GS11FHByyx S29GL01GS11TFByyx 120 V1 V2 S29GL01GS12DHByyx S29GL01GS12FHByyx S29GL01GS12TFByyx...

Page 102: ...rial 40 C to 85 C V Industrial Plus 40 C to 105 C A Automotive AEC Q100 Grade 3 40 C to 85 C B Automotive AEC Q100 Grade 2 40 C to 105 C Package Materials Set A Leaded Sn Pb balls BGA only F Halogen f...

Page 103: ...2S S29GL256S S29GL128S 15 Other Resources 15 1 Cypress Flash Memory Roadmap http www cypress com Flash Roadmap 15 2 Links to Software http www cypress com software and drivers cypress flash memory 15...

Page 104: ...of bit 7 in the Lock register B BWHA 07 08 2011 Performance Summary Updated table Typical Program and Erase Rates Secure Silicon Region ASO Corrected table Secure Silicon Region DQ1 Write to Buffer Ab...

Page 105: ...aximum Ratings table Added clarification DC Characteristics table Output High Voltage clarification Power Up Power Down Voltage and Timing table Added clarification Power Up figure Added clarification...

Page 106: ...Error Added clarification Protection Error Added clarification Write Buffer Abort Added clarification Performance Table Updated Embedded Algorithm Characteristics 40 C to 105 C table Device ID and Co...

Page 107: ...rence on page 55 Removed Address and Data Configuration Updated Command Summary on page 55 Updated Table 7 1 on page 55 to include ECC ASO Commands Updated Electrical Specifications on page 69 Added T...

Page 108: ...ted part numbers P 6061893 PRIT 03 30 2018 Updated Ordering Information on page 97 Updated Valid Combinations Standard on page 97 Updated Table 14 1 on page 97 Updated part numbers Updated Valid Combi...

Page 109: ...s the responsibility of the user of this document to properly design program and test the functionality and safety of any application made of this information and any resulting product Cypress product...

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