Document Number: 001-98285 Rev. *R
Page 19 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
4.
Read Operations
4.1
Asynchronous Read
Each read access may be made to any location in the memory (random access). Each random access is self-timed with the same
latency from CE# or address to valid data (t
ACC
or t
CE
).
4.2
Page Mode Read
Each random read accesses an entire 32-byte Page in parallel. Subsequent reads within the same Page have faster read access
speed. The Page is selected by the higher address bits (A
MAX
–A4), while the specific word of that page is selected by the least
significant address bits A3–A0. The higher address bits are kept constant and only A3–A0 changed to select a different word in the
same Page. This is an asynchronous access with data appearing on DQ15-DQ0 when CE# remains Low, OE# remains Low, and
the asynchronous Page access time (t
PACC
) is satisfied. If CE# goes High and returns Low for a subsequent access, a random read
access is performed and time is required (t
ACC
or t
CE
).
