Document Number: 001-98285 Rev. *R
Page 54 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
6.
Data Integrity
6.1
Erase Endurance
Note:
1. Each write command to a non-volatile register causes a P/E cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array
that is not P/E cycled.
6.2
Data Retention
Contact Cypress Sales or an FAE representative for additional information on the data integrity. An application note is available at
http://www.cypress.com/appnotes
Table 6.1
Erase Endurance
Parameter
Minimum
Unit
Program/Erase cycles per main Flash array sectors
100K
P/E cycle
Program/Erase cycles per PPB array or non-volatile register array
100K
P/E cycle
Table 6.2
Data Retention
Parameter
Test Conditions
Minimum Time
Unit
Data Retention Time
10K Program/Erase Cycles
20
Years
100K Program/Erase Cycles
2
Years
