Document Number: 001-98285 Rev. *R
Page 13 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
3.
Data Protection
The device offers several features to prevent malicious or accidental modification of any sector via hardware means.
3.1
Device Protection Methods
3.1.1
Power-Up Write Inhibit
RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During POR, the device can not be selected, will not
accept commands on the rising edge of WE#, and does not drive outputs. The Host Interface Controller (HIC) and Embedded
Algorithm Controller (EAC) are reset to their standby states, ready for reading array data, during POR. CE# or OE# must go to V
IH
before the end of POR (t
VCS
).
At the end of POR the device conditions are:
all internal configuration information is loaded,
the device is in read mode,
the Status Register is at default value,
all bits in the DYB ASO are set to un-protect all sectors,
the Write Buffer is loaded with all 1’s,
the EAC is in the standby state.
3.1.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the HIC does not accept any write cycles and the EAC resets. This protects data during V
CC
power-up
and power-down. The system must provide the proper signals to the control pins to prevent unintentional writes when V
CC
is greater
than V
LKO
.
3.2
Command Protection
Embedded Algorithms are initiated by writing command sequences into the EAC command memory. The command memory array is
not readable by the host system and has no ASO. Each host interface write is a command or part of a command sequence to the
device. The EAC examines the address and data in each write transfer to determine if the write is part of a legal command
sequence. When a legal command sequence is complete the EAC will initiate the appropriate EA.
Writing incorrect address or data values, or writing them in an improper sequence, will generally result in the EAC returning to its
Standby state. However, such an improper command sequence may place the device in an unknown state, in which case the
system must write the reset command, or possibly provide a hardware reset by driving the RESET# signal Low, to return the EAC to
its Standby state, ready for random read.
The address provided in each write may contain a bit pattern used to help identify the write as a command to the device. The upper
portion of the address may also select the sector address on which the command operation is to be performed. The Sector Address
(SA) includes A
MAX
through A16 flash address bits (system byte address signals a
max
through a17). A command bit pattern is located
in A10 to A0 flash address bits (system byte address signals a11 through a1).
The data in each write may be: a bit pattern used to help identify the write as a command, a code that identifies the command
operation to be performed, or supply information needed to perform the operation. See
commands accepted by the device.
3.3
Secure Silicon Region (OTP)
The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and permanently protected
from further changes i. e. it is a One Time Program (OTP) area. The SSR is 1024 bytes in length. It consists of 512 bytes for Factory
Locked Secure Silicon Region and 512 bytes for Customer Locked Secure Silicon Region.
