IEI Technology IOWA-MARK, User Manual

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IOWA-MARK Half-size CPU Card
PCI Dynamic Bursting [Enabled]
Use the PCI Dynamic Bursting option to enable every write transaction to go to the write
buffer and then allow burstable transactions then burst on the PCI bus and nonburstable
transactions do not.
Disabled PCI dynamic bursting does not occur
Enabled
(Default) PCI dynamic bursting does occur
PCI Master 0 WS Write [Enabled]
Use the PCI Master 0 WS Write option to enable zero wait states when writes to the PCI
occur.
Disabled
There are no zero wait states when there are writes to
the PCI bus
Enabled (Default) There are zero wait states when there are writes to the
PCI bus
PCI Delay Transaction [Disabled]
Use the PCI Delay Transaction option to support compliance with PCI specification
version 2.1. The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles.
Disabled
(Default) System not compliant with PCI specification version 2.1
Enabled System is compliant with PCI specification version 2.1
PCI #2 Access #1 Retry [Enabled]
Use the PCI #2 Access #1 Retry option to enable the buffer to continue to attempt to write
to the buffer until it is successful.