IBM CI5VGM Series, User Manual

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Chapter 3 BIOS Configuration
58 CI5VGM User’s Manual
CPU to PCI Write Buffer
When enabled, this option increases the efficiency of the PCI bus to and
speed up the execution in the processor. By default, this field is set to
Enabled .
PCI Dynamic Bursting
When enabled, this option combines several PCI cycles into one. By
default, this field is set to
Disabled .
PCI Master 0 WS Write
When enabled, this option increases the write cycle speed. By default,
this field is set to
Disabled .
PCI Delay Transaction
When enabled, this option delays PCI data transactions.
PCI Master Read Prefetch
When this item is enabled, the system is allowed to prefetch the next read
and initiate the next process.
PCI #2 Access #1 Retry
This item enables PCI#2 Access#1 attempts. By default, this field is set to
Disabled .
AGP Master 1 WS Write
When enabled, writes to the AGP bus are executed with 1 wait states. By
default, this field is set to
Enabled .
AGP Master 1 WS Read
When enabled, reads to the AGP bus are executed with 1 wait states. By
default, this field is set to
Disabled .
PCI IRQ Activated By
This field allows you to select the method by which the PCI bus
recognizes that an IRQ service is being requested by a device. The
default value is
Level .
Assign IRQ For USB / VGA
When enabled, an IRQ would be assigned to these items.