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HP Visualize J200, Reference Manual

The HP Visualize J200 Reference Manual is a comprehensive user guide that provides step-by-step instructions and detailed information on operating and maximizing the full potential of your HP Visualize J200. Download this manual for free from manualshive.com to access everything you need to know about this powerful product.

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3-17

J Class Technical Reference

Memory System

Average memory latency (E[W]) can be roughly estimated using the ACT (or average service time E[S].)
If Poisson transaction arrivals are assumed, then it may be found using the average issue rate (

) and

average retire rate (

) as follows:

E[W] = E[N] + E[S]

E[N] =

p

1- p

p =

E[S] = 1

< 1 (for a stable queue)

Steady-State Latency

For the purpose of making some comparisons, we will define the term “steady–state” latency. The term
steady–state refers to the condition when both the average issue rate and average retirement rate are
constant, resulting in the average number of queued entries also being constant.  Additionally,
steady–state refers to a condition where there is transaction flow balance –  the issue rate closely
approximates the retirement rate through the system.

The value of steady–state latency is primarily a function of queue depth and the average cycle time or
service time of the memory system for a given rate of contention. At this point, the latency observed at the
tail of the queue is equal to the Queue depth (E[N]) * Average Cycle (Service) Time (E[S].)  For an
average queue depth of 10, and an average cycle (service) time of 10 clocks, one can expect that the
latency for the last, or tail, transaction placed in the queue will be equal to 100 clocks.

The amount of time, or number of transactions required to reach the steady–state is a function of queue
depth and the ratio of the rate transactions are put input the queue verses being extracted from it. While the
average retirement rate is expected to be less than the issue rate (for a stable queue), there are periods of
time when the input rate exceeds that of the output rate, thereby causing transactions to accumulate in the
queue. They accumulate at a rate that is equal to the ratio of (issue/retire) – 1. If the output rate is .2
transaction per clock, and the input rate is 1 transaction every clock, a 5:1 ratio, then 5 – 1 = 4 transactions
will have accumulated in the queue for every transaction retired during that period of time.

Queue length affects system behavior in several ways. First, it determines the rate at which transactions
are issued – for a fixed rate of retirement. Transaction time–variance is also a factor. If the transaction
issue rate is not constant, and therefore time variant, then the queue length affects the rate at which
transactions may be issued. Pulsed or clustered transactions are one example of time variant behavior,
where a high rate of issue exists for short durations of time, but with an average issue rate that is generally
less than the retirement rate. For a given coefficient of variance, the larger the queue, the closer the issue
rate approximates the retirement rate. And, as the coefficient of variance increases, a greater queue length
is required to maintain a given issue rate.

Figure 3–9 plots latency as a function of bank and bus contention for a memory system with a queue
length of 10 entries, which is an average representation of the design. It is used to show that as the number
of banks and busses increase, reducing the Average Cycle Time, the average latency or E[W] per
transaction in the steady–state decreases.

Summary of Contents for Visualize J200

Page 1: ...For root Printed on Wed Sep 4 1996 12 44 27 From book skyhawk_tech_ref Document ch_1 Last saved on Wed Mar 13 1996 11 48 41 ...

Page 2: ...5 using 2 CPUs External Cache Instruction cache size Organization Bus width Instruction cache bus peak performance Data cache size Organization Bus width Data cache bus peak performance 256 KByte 1 MByte cpu J210XC only Direct mapped 64 bits 960MB sec I fetch 8 byte 256 KByte 1 MByte cpu J210XC only Direct mapped 64 bits 960MB sec load 8 byte 960 MB sec single store 8 byte Time source Battery back...

Page 3: ...3 94 7 GPC PLBsurf93 95 4 Xmark93 11 0 GPC PLBwire93 102 1 GPC PLBsurf93 138 5 Power supply max input power 664 Watts Max Continuous output power 484 Watts Five DC output voltages 5V 4 5V 12V 3 4V and 12V Also 15V auxiliary for standby Mass storage Up to two of the following 1GB low profile 3 5 inch Fast Wide Differential SCSI hard disk drive 2GB low profile 3 5 inch Fast Wide Differential SCSI ha...

Page 4: ...e 90 meter DDS data cassettes HP92283K Package of two cleaning cassettes Floppy Disk Drive HP A4283A SCSI Floppy Drive HP92192X High Density Micro Flexible Disks 1 44MB Formatted Capacity box of ten diskettes System Graphics The supported monitors are A4032A 17 inch 1280x1024 color monitor A4033A 20 inch 1280x1024 color monitor The supported graphics boards are A4077A 2D color graphics A4070A HCRX...

Page 5: ...ds using gold plated plugs available through audio retailers for best quality recording and playback through the external connectors The following is a summary of the workstation audio features Audio Features Programmable sample rates 8kHz 16kHz 32kHz 48kHz 11 025kHz 22 05kHz and 44 1kHz Programmable output attenuation 0 to 96dB in 1 5dB steps Programmable input gain 0 to 22 5dB in 1 5dB steps Inp...

Page 6: ... N then n 61 6 significant bits or in other words about 6 bits of noise 10 Microphone 22mVpk 1kohm Keyboard Interfaces The J Class workstation provides keyboard interfaces that allow either PS 2 or ITF keyboards Consult the documentation that accompanies each input device for specific information concerning its use PS 2 Keyboard Interfaces The PS 2 connectors provide an interface for the keyboard ...

Page 7: ...N Transceiver HP 30241A 10Base4 ThickLAN MAU HP 28692A ThinLAN Hub Plus HP 28673A 10 10 LAN Bridge HP 28683A Fiber Optic Transceiver RS 232 Serial I O Interfaces The RS 232 Serial I O SIO ports on the J Class accept a variety of pointing devices or peripheral devices Peripheral devices include printers plotters modems and scanners Consult the documentation that accompanies each peripheral device f...

Page 8: ...iguration you must use an active SCSI terminator at the last external device on the SCSI bus All other devices external or internal must not be terminated Use only HP K2291 terminators to ensure reliable system operation Recommended SCSI 2 mass storage device bus addresses are listed in Table 1 5 and SCSI interface technical information is listed in Table 1 6 Unit or Mass Storage Device Recommende...

Page 9: ... end of the cable Fast Wide Differential SCSI 3 Fast wide SCSI is an extension to the existing 8 bit single ended SCSI Fast differential indicates that signals on the SCSI bus are differentially driven and terminated and capable of a 10 MHz clock rate Wide indicates that there are 16 data bits on the SCSI bus The fast wide SCSI bus is specified at a peak synchronous transfer rate of 20 MB sec The ...

Page 10: ...d processors without moving the system Figure 1 1 shows the front view of the system There is a Power Switch with an LED to indicate that the system is on off and an LCD panel that informs users of the system s status In the case of a failure the LCD indicates the failure code System LCD System Power Switch System Power LED Figure 1 1 System Unit Front Panel Controls Figure 1 2 shows a peripheral ...

Page 11: ...U s that are accessed from the back of the system the I O card and EISA cardcage There are two external SCSI connectors available for external devices to be used with this product Operating System HP UX HP UX 9 05 and 10 0 are supported on the Model J200 and J210 workstations HP UX is booted from an internal hard disk drive factory installed with Instant Ignition HP UX can also be installed from e...

Page 12: ...om ponent and all Optional Components except XTI only HP UX 10 01 Model J210XC only more info need ed X Window System Version 11 Release 5 X11R5 OSF Motif 1 2 Languages C ANSI C C FORTRAN 9000 Pascal PA RISC 1 1 Assembler COBOL User Interface and Graphics Libraries HP VUE 3 0 X11R5 PEX PHIGS Starbase capabilities HP PowerShade Product Identification A label on the back of the J Class workstation l...

Page 13: ...1 GSC interface for use with CRX 48Z HP A4070 69504 HCRX 8 HP A4071 69507 HCRX 24 HP A4081 69009 Color Graphics Card Board Nonexchange Part Numbers HP A4081 60004 I O Connector PCA HP A4081 66011 Jumper PCA HP A4081 66007 SCSI Disk PCA Support Documentation Table 1 8 and Table 1 9 list the service and support documentation Table 1 8 Service Documentation Manual Title Part Number Service Handbook J...

Page 14: ...uide HP UX 9 05 Series 700 Release Notes Read Me First HP UX 9 05 HP UX 9 05 PCO Read Me Installing HP UX Installing Peripherals HP UX 10 0 Manuals Using your HP Workstation HP Vue 3 0 User s Guide HP Vue Quick Start Guide HP UX 10 0 Release Notes Read Me First HP UX 10 0 s700 Installing HP UX 10 0 Configuring HP UX for Peripherals 10 0 HP UX 10 01 Manuals A4081 90601 A4081 90600 A4277 90600 A4081...

Page 15: ...y Underwriters Laboratories UL listed UL 1950 Canadian Standards Assoc CSA certified CSA 22 2 950M TUV license to EN60950 EMKO TUE 74 DK203 Electromagnetic Compatibility EMC Directive EN55022 CISPR 22 Class B EN55024 2 IEC801 2 EN55024 3 IEC801 3 EN55024 4 IEC801 4 Ergonomics TUV ZH1 618 ISO9241 90 270 EEC System Processing Unit Physical Dimensions See Figure 1 4 Weight Min configuration 80 lbs 36...

Page 16: ...on operating 5 25 milligauss dc at 15 ft Electromagnetic Interference EMI Emissions FCC Class B Susceptibility FCC Class B Electrostatic Discharge Air discharge 0 15 kV no effect Contact discharge 0 3 kV no effect Humidity Non condensing Operating 15 to 80 Leakage Current less than 3 5 mA Shock Operating 20 g at less than 3 ms 1 2 sine in normal axis with no hard errors Non operating 80 g at less ...

Page 17: ... of the J Class with and without mass storage Table 1 10 AFR and MTBF Product Configuration AFR MTBF J Class 32 MB no mass storage 22 0 39 818 J Class 32 MB with mass storage 25 5 34 350 Projected Failure Rate is the mature AFR estimated from the failure rates of the components of the product The Estimated Long Term Annualized Failure Rate is a future projection of an average realistic failure rat...

Page 18: ... be easily removed from the front of the chassis It contains two removal drives and two hard drives It has two external connectors FW SE for external to chassis connections It connects to the back plane through a daughter card in the bay The following is a detailed specification of this section NOTICE Removal of the peripheral assembly is for ease of maintenance and upgrading It is NOT for data se...

Page 19: ...s two 80 mm fans designed to deliver the proper airflow to all sections in the system Power is distributed through blind mate interconnects to the system backplane minimizing the number of internal power cables and easing manufacturing and field servicing of the system The power system budget is shown in Chapter 7 of this document There are two voltage regulators on the system board One converts 5...

Page 20: ...ogic VDD Vss 0 min 6 5v max Power For LCD VDD Vo 0 min 5 0v max Power Supply Current VDD 5 0v 1 0ma typ 3 0 ma max Air Flow 80 mm 3 14 in 160 mm 6 3 in 80 mm 3 14 in 80 mm 3 14 in 80 mm 3 14 in NOTE Clearances given are for the minimum required air flow Figure 1 5 J Class Air Flow ...

Page 21: ...For root Printed on Wed Sep 4 1996 12 44 36 From book skyhawk_tech_ref Document ch_2 Last saved on Fri Apr 19 1996 11 56 05 ...

Page 22: ...e system board contains Two processor modules 16 Memory SIMMs This board can be accessed and replaced from front of the system There is also a daughter board that has the power ON OFF and LCD for system status The following is the detailed specification of this board FRUs PART NUMBER System Board A4081 66012 Processor Module A2375 66056 Model J200 100 MHz Processor Module A2375 66057 Model J210 12...

Page 23: ... CACHE CPU 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM Slave Memory 208 MQUAD 432 PGA PDH Processor Module Processor Module Controller Slave Memory 208 MQUAD Controller Slave Memory 208 MQUAD Controller Slave Memory 208 MQUAD Controller 4 EISA Card Slots GRAPHICS 3 GSC Card Slots System Motherboard EISA PCA System Unit Functional Block Diagram Interface Specifications T...

Page 24: ...d rate 19 2 K Word size 5 to 8 bits Parity number of stop bits Odd even one zero none Device Type 1 per interface connector Connector Type 9 pin male D sub connector HP Parallel The Parallel Interface is an 8 bit parallel synchronous interface commonly used for printers The hardware implementation has bidirectional capabilities compatible with PS 2 standards also know as Centronics R interface The...

Page 25: ...struction and Data cache and a bus interface Different performance points can be achieved by adjusting three factors processor clock frequency bus clock frequency and cache size Introduction The electrical interface between the CPU module and the rest of the system is composed of power clocks the interconnect bus interface and test interface Most power and ground and all logical signals are routed...

Page 26: ...ce Table 2 5 specifies the interconnect bus signals bussed on and off the CPU module Table 2 5 Interconnect Bus Interface Signal List Signal Signal Count Direction Comments ADDR_DATA 0 63 64 Bi dir ADDR_PAR 0 1 2 Bi dir ADDR_VALID 1 Bi dir ARB_IN 0 2 3 Input ARB_OUT 1 Output CLIENT_ID 0 3 4 Static Input Tied on system board CLIENT_OP 0 2 3 Input COH 0 1 2 Output Point to Point CTL_PAR 1 Bi dir DAT...

Page 27: ... system with a system clock frequency that is incompatible with the module Please refer to Tables 2 11 2 12 2 13 and 2 14 for a further description of the configuration status byte Table 2 7 Module Configuration Status Byte Status 0 7 0 1 2 3 4 5 6 7 Cache Configuration Operating Frequency Operating Voltage Status 0 5 are supplied to the Processor Dependent Hardware PDH PDH is able to detect the p...

Page 28: ...r system which senses the configuration before supplying power to the system Each of the bits is pulled high through a resistor in the power supply The CPU module ties the bits which should be zero to ground through a 0 ohm resistor Table 2 11 Operating Voltage Configuration Bits Status 6 7 Nominal Processor Operating Voltage 6 7 Operating Voltage 0 0 5 0 Volts 0 1 4 4 Volts 1 0 Reserved J200 and ...

Page 29: ... for both technical and commercial applications including increased frequency instruction and data cache prefetching enhanced superscalar execution and enhanced multiprocessor support The PA7200 connects directly to a new split transaction 768 Megabytes second multiprocessor memory and I O bus This enables high performance multiprocessor systems without requiring additional processor interface com...

Page 30: ...on chip data cache 64 cache lines FIFO queue Accessed in parallel with external cache 3 data prefetch modes 1 No prefetch 2 Only on modify after miss 3 Any miss or first access 1 miss and up to 4 prefetches in parallel No allocate cache hint Instruction prefetch buffer 1 cache line TLB Features Feature Description MMU 120 entry unified I D TLB Fully associative NRU replacement 4K page size TLB 1 e...

Page 31: ...t be a certain combination Prior to writing the double word out to cache the CPU determines if the instructions can be bundled If so the predecoded information is written out to the cache along with the double word The double word in the I Cache is protected by word parity In the case of an I cache parity error the line is marked invalid and the CPU must fetch the line from memory Reads and writes...

Page 32: ...s Features The interconnect bus has the following features Provides a price performance competitive bus for 1 4 way maximum of 2 way on J Class multiprocessing for high end workstations and mid range servers Provides leadership effective memory latency Minimizes interface complexity Spans both technical and commercial markets Supports cache coherent I O Performs multiple outstanding transactions p...

Page 33: ... with the issuing module s MASTER_ID and a transaction ID such that the combination of MASTER_ID transaction ID and return type are unique for the duration of the transaction The data response is identified by the same MASTER_ID and transaction ID so that an extra address cycle is not needed for the data return Decoupled Coherency Reporting Each module can report cache coherency CCC status on cohe...

Page 34: ...ransactions Up to 64 outstanding transactions per client supported 32 byte cache line supported restricted by memory and IO design Snoopy coherency protocol Coherent I O supported Address Data and Control parity protection Supports EISA as a Lower I O Bus ...

Page 35: ...For root Printed on Wed Sep 4 1996 12 44 46 From book skyhawk_tech_ref Document ch_3 Last saved on Mon Apr 22 1996 09 12 28 ...

Page 36: ...ystem uses multiple independently controlled sequentially interleaved banks of Fast Page Mode DRAM memory to produce up to 768 MB per second 960 MB per second with EDO DRAM of maximum data throughput Multiple memory banks cycle at a rate of 12 MHz 15 MHz for EDO per 32 bytes of data on 2 independent DRAM Data buses The J Class memory system uses conventional asynchronous DRAM technology in the mem...

Page 37: ...ry banks are connected to the DRAM Data Path MUX chips via 16 byte data buses RDA_H RDB_H The RDA and RDB buses can deliver two 16 byte pieces of data every four five or six 60MHz cycles depending on whether the transaction is a EDO read a non EDO read or a write respectively These correspond to peak RDx_H bandwidths of 480MB s 384MB s or 320MB s respectively However the RDx_H buses are independen...

Page 38: ... 72 30MHz 72 30MHz 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM 72b SIMM Master DRAM Data Path Mux Chips Multibank RDB_H RDA_H 131 Signals 208 MQUAD 131 Signals 208 MQUAD 131 Signals 208 MQUAD 2 Half Banks SIMM 4 Banks Halcon 2 Banks 2 SIMMs SA_H TC_H TV_H SRESET_L TACK MSI_PAR MREADA_H MWRITEA_H MREADB_H MWRITEB_H 16 Banks Total Memory Controller DRAM Data Path Mux Control A DRA...

Page 39: ...mory System The master memory controller is the primary interface between the interconnect bus the system backplane andthememoryarray Ithelpsmanagetheprocessor memory I Ointerconnectbus protocol including cache coherency and arbitration provides the programmatic interface for system memory generates and checks memory ECC provides buffering of memory write and read transactions from the interconnec...

Page 40: ...emory Banks The design supports from one to 16 independent banks of memory Each bank consists of a 16 byte wide arrayofmemorywhichisaccessedusingapage modecycletofetchout32bytesofdata cacheline The memory bank depth is a function of the DRAM density and its organization for example 16Mbit x 4 8Mbit x 8 Multiple parallel banks of memory are used collectively to produce very high data throughputs Ea...

Page 41: ...RAM 4Mbit 64 MB 4M x 4 DRAM 16Mbit Performance and Interleaving Memory SIMMs Note Interleaving is only performed across SIMMs of the same size To get the best memory performance load SIMMs of all the same size When SIMMs of different sizes are installed in a system use the following guidelines 1 Load SIMM pairs of the same size starting from SIMM pair 1 to SIMM pair x starting with the larger size...

Page 42: ...istream pipeline decoupled by queues at critical points Transactions are buffered at several points within the Master Memory Controller and the multibank DRAM Controller Figure 3 4 shows a diagram of queue positions as well as idle issue rates and idle latency for each component in the memory system ...

Page 43: ...mory System Queuing and Staging Points Memory Queuing Each individual multibank DRAM Controller has its own queue However all multibank DRAM Controller queues operate in synchronous harmony with each multibank DRAM Controller tracking the progress of others through its own queue In essence they appear as one This implementation greatly simplifies the Master Slave Interface MSI protocol but constra...

Page 44: ...T2 T4 T6 T1 T3 T5 T7 T9 T1 T3 T5 T7 T9 T11 T12 T13 T14 Access Latency Precharge DRAM Data 32 bytes Access Latency Precharge DRAM Data 32 bytes Access Latency Precharge DRAM Data 32 bytes Access Latency Precharge DRAM Data 32 bytes DRAM Data 32 bytes DRAM Data 32 bytes DRAM Data 32 bytes DRAM Data 32 bytes Access Latency Precharge DRAM Data 32 bytes DRAM Data 32 bytes Access Latency Precharge DRAM ...

Page 45: ... to execute transactions in parallel are memory bank contention and DRAM Data bus contention Memory Bank Contention Memory bank contention results from two memory transactions contending for usage of the same memory bank Under this circumstance the losing transaction or second one in is delayed until the prior transaction completes Because transactions are constrained to complete in exact order in...

Page 46: ...uential cache lines will minimize the potential for bank conflicts and maximize the memory system s throughput The worst performing reference pattern is one that has a stride equivalent to the number of memory banks causing each reference to continually map to one particular bank Most other patterns fall into the random uniform access case shown here This modest approach to understand the memory s...

Page 47: ...or retirement rate of the memory system affects the average latency in a queued system An increased cycle time also increases the time a transaction sits in queue thereby increasing the time it takes to complete the transaction from the point of issue The simplest and most common tactic used in characterizing memory system performance is to state maximum bandwidth and idle system latency values Wh...

Page 48: ... or Average Cycle Time ACT per transaction through the memory system can be derived from the following The above formula reflects resource contention by representing it in terms of numbers of banks and busses Estimating Average Memory Cycle Times and Bandwidth With a method stated for determining average memory system cycle time the behavior of the memory system as a function of the number of bank...

Page 49: ...Cycle Time for Number of Banks ORGANIZATION OF BANKS ON BUSSES MAY RESTRICT BANDWIDTH 2 DRAM Data Bus 1 DRAM Data Bus 0 10 20 30 40 50 60 70 80 90 100 110 0 1 2 3 4 5 6 7 8 9 10 2 Banks 8 Banks 16 Banks 4 Banks Figure 3 7 Data Cycle Time Versus Increasing Fast Page Mode DRAM Banks and Busses Figure 3 8 shows the bandwidth range that the memory system is capable of producing for the conditions spec...

Page 50: ...ations along with 1 and 2 DRAM Data busses when applicable are shown The top horizontal axis shows the absolute minimum cycle time possible for the combination of memory banks It should be pointed out that the above plotted numbers do not reflect the effect of queue size and transaction time variance on issue rate which is a primary factor used in determining total system cycle time To understand ...

Page 51: ...anks significantly affects the ACT of the memory system As more banks are added the ACT asymptotically approaches the minimum cycle time In general the memory system depends on large numbers of memory banks to generate high data throughputs via reduced bank contention In a typical 128 MB configuration it is possible that only two banks of memory are available when using 16 Mbit 4Mbit x 4 DRAM tech...

Page 52: ...racted from it While the average retirement rate is expected to be less than the issue rate for a stable queue there are periods of time when the input rate exceeds that of the output rate thereby causing transactions to accumulate in the queue They accumulate at a rate that is equal to the ratio of issue retire 1 If the output rate is 2 transaction per clock and the input rate is 1 transaction ev...

Page 53: ... 50 60 70 80 90 100 110 Clocks of Latency per Data Cycle 60 MHz Bank Address Conflicts 0 Bus Conflicts 100 2 Banks 4 Banks 8 Banks 16 Banks 1 Bank 2 DRAM Data Bus 1 DRAM Data Bus 2 DRAM Data Bus 1 DRAM Data Bus Figure 3 9 Steady State latency for EDO DRAM This assumes a FULL 10 entry memory queue ...

Page 54: ...For root Printed on Wed Sep 4 1996 12 44 56 From book skyhawk_tech_ref Document ch_4 Last saved on Tue Mar 12 1996 09 01 01 ...

Page 55: ...core of the J Class I O system is the U2 chip U2 connects to the CPU module via the interconnect bus and all the I O devices via one of two GSC buses These buses are broken down on the J Class Mother Board schematics as K0_ signal_name and K1_ signal_name U2 also has the EEPROM access and Real Time Clock ports This section covers how J Class connected U2 in the system J Class generates its GSC bus...

Page 56: ...J Class I O System Architecture Graphics System Connect GSC GSC is an interconnect consisting primarily of 48 signals and designed to support a wide range of functions ranging from DMA I O devices to host manipulated graphics controllers Some GSC features include GSC Features 32 bit shared address data bus up to 40 MHz operation Semaphore support Lock signal Address Data bus parity detection Singl...

Page 57: ...hat new devices can be added to the system without the need for jumpers A Slot ID feature has been added to the GSC hardware definition to allow for up to 16 GSC devices per GSC bus The inclusion of the SLOT ID accomplishes the following The inclusion of a SLOT ID in GSC has the benefit of allowing address space selection to be accomplished without jumper selection Also it is especially important ...

Page 58: ... 1 1 ParDevCtl slv 802 1 1 NwrRd IrqEnb NSlin Ninit Autofd Strobe slv 803 Not Used undefined ModeCtl slv 804 Mode 2 Mode 1 Mode 0 Biden fNstb 0 0 0 IECtlStat slv 805 dmaInt 0 Nbsy Int Nack Int ack Nbsy peInt slctInt errInt TDC0 slv 806 Timing Delay Value 0 obsolete TDC1 slv 807 Timing Delay Value 1 slv 0XFFD02000 Parallel Port DMA Controller The J Class parallel port DMA controller emulates an EIS...

Page 59: ...read write 1 Current Address High Page register drs 0XFFD03000 dma 0XFFD01000 How Parallel Port DMA Works The J Class Parallel Port DMA controller transfers data from memory to the parallel port without disturbing the CPU until the transfer sequence is complete To start a sequence the DMA channel needs to have a beginning address and byte count placed into the proper registers Given that the mode ...

Page 60: ...ount register will have the value indicating the data just read had been processed this should help in the debug process RS 232 Registers Table 4 3 shows suggested connector pinouts for the RS 232 interface Both a nine position male D connector such as those used in PC products and a twenty five position female D connector such as those used in traditional workstations are shown Table 4 3 RS 232 C...

Page 61: ... R RESET Interface reset register 0x00 0xXX W RCVDATA Received data register 0x04 0xXX R XMTDATA Transmit data register 0x04 0xXX W CONTROL Control register read write 0x08 0x00 note 2 R W STATUS Status register read only 0x0c 0x00 R Note 1 Each PS2 device returns a unique hardwired ID code in bits 3 0 of ID Note 2 Resetting the block disables it ID Register Table 4 5 shows the PS 2 ID register Ta...

Page 62: ...share the bandwidth of the interconnect Because it is not possible to decouple the bandwidth of the EISA and GSC devices at this time it may be important to have the appropriate expectations regarding the distribution of GSC bandwidth if one considers using EISA for higher bandwidth applications 0 10 20 30 40 50 60 70 80 90 100 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 EISA DMA Master Ban...

Page 63: ...m RAM CPU reads from and writes to the Lock Control Register this register lets the CPU run a sequence of locked undivided cycles on the EISA bus CPU reads from and writes to the FIFO Enable Register this register lets the CPU flush the inbound buffer and clear the outbound buffer or disable data buffering altogether CPU reads from the Interrupt Acknowledge Register this is the way the CPU runs in...

Page 64: ...6 EISA Converter EPCU EBCU reset reset irq nmi bus req bus ack bus ack bus req control ctrl in ctrl out data out data in address data path control data reset irq reset irq address bus ack arbitration control address bus req control address inter chip communication TI s TI s nmi irq address address nmi Figure 4 4 GSC to EISA Interface Block Diagram ...

Page 65: ...Control Reg IRQ Acknowledge inaccessible inaccessible inaccessible 0000 FFFF 0000000 address scrambling 0007FFF 0008000 000FFFF 0010000 004FFFF 0050000 00FFFFF 0100000 03BFFFF 03C0000 FFFFFFF to Control E ISA I O E ISA Memory EISA ISA I O ISA 20 Address Bit Memory ISA 24 Address Bit Memory EISA 32 Address Bit Memory FC4FF000 FC011001 FIFO Enable Reg FC01E001 Status Reg FC012001 Bus Concurrency Reg...

Page 66: ... E ISA Master 00000000 00500000 00FFFFFF 01000000 03BFFFFF 03C00000 FFFFFFFF System Memory Access E ISA Memory Memory Address Slave Access 00100000 00080000 00000000 FFFFFFFF Address Mapper EISA 32 Address Bit Memory inaccessible from CPU EISA 32 Address Bit Memory accessible ISA 24 Address Bit Memory accessible ISA 20 bit Mem from CPU from CPU 000FFFFF Figure 4 6 Accesses from an EISA Master ...

Page 67: ... 2 2 2 1 2 2 2 1 1 2 1 1 3 1 1 3 1 1 4 2 This matrix ensures that at least one GSC slot remains free for non graphics use Audio Subsystem J Class provides stereo quality audio output with a 16 bit codec The codec combines quality stereo A D converters for microphone and line input levels as well as D A converters for driving headset and the speaker The input sampling rate and format are programmab...

Page 68: ... for this code Both the parts used are of AMD AM29040 120JC type The in circuit programming of these parts is controlled by the U2 chip and updates are performed by a software update program which can be run off a tape drive or over the LAN The Scratch RAM is a 32k x 8 SRAM PN HM62256ALFP 101 This again is controlled by the U2 chip and can be written to by either the firmware or the Operating Syst...

Page 69: ...For root Printed on Wed Sep 4 1996 12 45 02 From book skyhawk_tech_ref Document ch_5 Last saved on Tue Mar 12 1996 09 01 03 ...

Page 70: ... documentation that accompanies each SCSI device for specific information concerning its use Refer to Appendix C of the J Class Owner s Guide for information about connecting SCSI devices to the workstation Hewlett Packard only supports SCSI devices that were designed for the J Class workstation Third party SCSI drives are not supported but if they meet SCSI II specifications they should work on t...

Page 71: ...Data Bus Data Bus Data Bus Data Bus Data Bus MSB Data Bus Parity Terminator Power Reserved Not Used GND Indicates message available for drive Not Used GND Signal indicating bus is in use Data Command transfer handshake Or tied signal indicating reset condition Indicates message phase Signal indicating selection reselection phase Indicates whether control or data information is on data bus DataComm...

Page 72: ... connector on both ends The last device connected to the SCSI bus must be terminated with a SCSI terminator All of the devices listed ship without terminators If you do not already have a SCSI terminator you must order terminator K2291 for 50 pin connectors or C2905A for 68 pin connectors from Hewlett Packard Note When attaching external SCSI devices be sure to terminate the last device on the ext...

Page 73: ...For root Printed on Wed Sep 4 1996 12 45 05 From book skyhawk_tech_ref Document ch_6 Last saved on Tue Mar 12 1996 09 01 06 ...

Page 74: ...t per photomasters 5955 6670 HP company logotype 12 1 2 inches 5955 6677 ISO Symbols Vertical 5955 6673 Environmental statement 5955 6691 Lifting Limitation Graphic 100 lbs 45 kg 016691 Open Me First A1630 84023 2 Install Instruct Encl A1658 84011 2 Disk Drive Warning A1658 84021 2 CE Mark no year indicated AW A1658 84037 11 AW PA RISC Powered size 130 AW A1658 84040 11 Unpacking Pictorial AW A165...

Page 75: ... Figure 6 2 Package Tray Bottom View Figure 6 3 Unpacking Pictorial ...

Page 76: ... 1 1 0 2 1 1 0 2 0 0 3 Figure 6 4 Package Pallet ...

Page 77: ...For root Printed on Wed Sep 4 1996 12 45 09 From book skyhawk_tech_ref Document ch_7 Last saved on Tue Mar 12 1996 09 01 07 ...

Page 78: ...ycling AC power or the PCL L switch after the fault condition is removed Fans are included as an integral part of the power supply to cool the system and power supply The system is designed so the fans provide maximum cooling with all the covers in place Power Supply Specifications Table 7 1 Table 7 2 and Table 7 3 show the power supply output specifications input specifications and demand Table 7...

Page 79: ... 203 0 W LAN 5 0 SCSI Adapter 3 0 Multi Function I O 2 5 RS232 Centronics 1 5 Multimedia 4 9 HP HIL 10 0 Drives 2 x 2 GB FW 36 8 Drive CD ROM 6 0 Drive Floppy or DDS 6 0 Fans 7 2 Graphics and keyboard Interface 8 0 EISA 110 2 Total Power 407 6 W Electrical Information Output Connectors There are three panel mount output connectors used P1 P2 and P3 P1 housing Molex 15 06 0180 18 position P2 P3 hou...

Page 80: ...For root Printed on Wed Sep 4 1996 12 45 45 From book skyhawk_tech_ref Document ch_8 Last saved on Tue Mar 12 1996 09 02 21 ...

Page 81: ...style cable The physical characteristics are as follows Length 467 mm 18 4 in Width 184 mm 7 25 in Height 48 mm 1 9 in Weight 1 09 kg 2 4 lb Japanese version Length 455 7 mm 17 95 in Width 164 51 mm 6 48 in Height 38 07 mm 1 50 in Keyboard Layout Figures 6 1 through 6 14 show the 14 keyboard key layouts available for the J Class workstations ...

Page 82: ... Figure 8 1 Danish Keyboard ...

Page 83: ... Figure 8 2 French Keyboard ...

Page 84: ... Figure 8 3 German Keyboard ...

Page 85: ... Figure 8 4 Italian Keyboard ...

Page 86: ... Figure 8 5 Japanese Keyboard ...

Page 87: ... Figure 8 6 Korean Keyboard ...

Page 88: ... Figure 8 7 Norwegian Keyboard ...

Page 89: ... Figure 8 8 Spanish Keyboard ...

Page 90: ...8 10 Keyboard Layouts J Class Technical Reference Figure 8 9 Swedish Keyboard ...

Page 91: ... Figure 8 10 Swiss Keyboard ...

Page 92: ...8 12 Keyboard Layouts J Class Technical Reference Figure 8 11 Taiwanese Keyboard ...

Page 93: ...8 13 J Class Technical Reference Keyboard Layouts Figure 8 12 United Kingdom Keyboard ...

Page 94: ...8 14 Keyboard Layouts J Class Technical Reference Figure 8 13 United States Keyboard ...

Page 95: ...For root Printed on Wed Sep 4 1996 12 46 15 From book skyhawk_tech_ref Document ch_9 Last saved on Tue Mar 12 1996 09 02 22 ...

Page 96: ...ACCESS KEY NC NC 12V M 10 LOCK RESERVED GROUND RESERVED BE 3 ACCESS KEY BE 2 BE 0 GROUND 5V LA 29 GROUND LA 26 LA 24 ACCESS KEY LA 16 LA 14 5V 5V GROUND LA 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GROUND RESDRV 5V IRQ 9 5V DRQ 2 12V NOWS 12V GROUND SMWTC SMRDC IOWC IORC DAK 3 DRQ 3 DAK 1 DRQ 1 REFRESH BCLK IRQ 7 IRQ 6 IRQ 5 IRQ 4 IRQ 3 DAK 2 T C BALE 5...

Page 97: ...RST MSBURST W R GROUND RESERVED RESERVED RESERVED GROUND ACCESS KEY BE 1 LA 31 GROUND LA 30 LA 28 LA 27 LA 25 GROUND ACCESS KEY LA 15 LA 13 LA 12 LA 11 GROUND LA 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOCHK D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CHRDY AENx SA 19 SA 18 SA 17 SA 16 SA 15 SA 14 SA 13 SA 12 SA 11 SA 10 SA 9 SA 8 SA 7 SA 6 SA 5 SA 4 SA 3 SA 2 SA ...

Page 98: ...1 12 13 14 15 16 17 18 M16 IO16 IRQ 10 IRQ 11 IRQ 12 IRQ 13 IRQ 14 DAK 0 DRQ 0 DAK 5 DRQ 5 DAK 6 DRQ 6 DAK 7 DRQ 7 5V MASTER16 GROUND Row G Row C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LA 7 GROUND LA 4 LA 3 GROUND ACCESS KEY D 17 D 19 D 20 D 22 GROUND D 25 D 26 D 28 ACCESS KEY GROUND D 30 D 31 MREQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SBHE LA 23 LA 22 LA 21 LA 20 LA 19 LA 18 LA 17...

Page 99: ...D1 42 FW_SD1 9 FW_SD2 43 FW_SD2 10 FW_SD3 44 FW_SD3 11 FW_SD4 45 FW_SD4 12 FW_SD5 46 FW_SD5 13 FW_SD6 47 FW_SD6 14 FW_SD7 48 FW_SD7 15 FW_SP0 49 FW_SP0 16 FW_DIFFSENS 50 Gnd 17 FW_TERM POWER 51 FW_TERM POWER 18 FW_TERM POWER 52 FW_TERM POWER 19 not connected 53 not connected 20 FW_SATN 54 FW_SATN 21 Gnd 55 Gnd 22 FW_SBSY 56 FW_SBSY 23 FW_SACK 57 FW_SACK 24 FW_SRST 58 FW_SRST 25 FW_SMSG 59 FW_SMSG ...

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