4
I/O System
J Class systems support three distinct classes of I/O: namely Core I/O, Industry Standard Connectivity
I/O, and high–performance proprietary I/O. Core I/O, or built–in I/O, is leveraged from the concepts of
earlier workstations. Core I/O is that set of functions that are likely to be required by the majority of users,
and therefore can be offered at reduced costs by removing them as options. These systems rely on EISA to
serve all of the general purpose, OEM or 3rd party, connectivity I/O needs. When higher performance is
needed, HP’s proprietary GSC (Graphics System Connect) is available for throughputs exceeding EISA’s
capability.
Core I/O
The built–in, core I/O features in J Class include:
5 MB/sec SCSI–2; NCR53C710
10 Mbit/sec 802.3; Intel82596
Centronics Parallel port
2 PS/2 ports for keyboard and mouse
Stereo Audio
RS232 (2 ports)
HIL
20 MB/sec SCSI–3; NCR53C720
U2
The core of the J Class I/O system is the U2 chip. U2 connects to the CPU module via the interconnect bus
and all the I/O devices via one of two GSC buses. These buses are broken down on the J Class Mother
Board schematics as K0_(signal_name) and K1_(signal_name). U2 also has the EEPROM access and
Real Time Clock ports. This section covers how J Class connected U2 in the system.
J Class generates its GSC buses and its Processor–Dependent Hardware I/O (PROM access and Real
Time Clock ports) using the U2 chip. U2 connects the CPU–Memory–I/O interconnect with two GSC
buses.
U2 incorporates two identical 32–bit GSC bus ports. Each bus port consists of 3 basic elements: the clock
circuitry, arbitration logic, and the data transfer protocol logic. The clocking, arbitration, and data transfer
on U2’s two GSC ports are independent. U2 is the host on each of the GSC buses. U2 will master
transactions directed to GSC guests operating as slaves, and will be the slave in transactions mastered by
GSC guests (guest to guest transfers are not supported).
Figure 4–1 shows the J Class I/O system architecture.
Summary of Contents for Visualize J200
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