HP Visualize J200, Reference Manual

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3-4 Memory System
J Class Technical Reference
Master/Slave Interconnect (MSI) - 60 MHz
45
Processor-Memory-I/O Interconnect Bus - 120 MHz
Master
Memory
Controller
SIMM
SIMM
SIMM
SIMM
SIMM
SIMM
SIMM
SIMM
Memory Data Path Mux
45
144 144
16-SLOT
MEMORY INTERFACE
1024 Mbytes (16 mbit DRAM)
Double Sided SIMM
144
MUX Data Bus - 60 MHz
DRAM
Controller
Master/Slave Interconnect (MSI) - 60 MHz
DRAM Data Bus - 30 MHz DRAM Data Bus - 30 MHz
64
DRAM
Controller
DRAM
Controller
DRAM
Controller
Figure 3–2. J Class Memory System
The master memory controller is the primary interface between the interconnect bus, the system
backplane, and the memory array. It helps manage the processor–memory–I/O interconnect bus protocol,
including cache coherency and arbitration, provides the programmatic interface for system memory,
generates and checks memory ECC, provides buffering of memory write and read transactions from the
interconnect bus to the DRAM Controllers, and provides the primary high–speed memory data path to the
interconnect bus. It is implemented in a 432–pin CPGA and operates most of it’s internal circuitry at
one–half the interconnect bus frequency – the interconnect bus interface operates at 120 MHz (nominal.)