HP Visualize J200, Reference Manual

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3-15 J Class Technical Reference Memory System
0
10
20
30
40
50
60
70
80
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100
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0 1 2 3 4 5 6 7 8 9 10
Clocks per Data Cycle @ 60 MHz (32-byte line)
% Bank
Address
Contention
192 MB/S 240 MB/S 480 MB/S 960 MB/S
0 % Bus Conflicts 100
320 MB/S
2 Banks 1 Bank 4 Banks 8 Banks
Minimum Cycle Time for Number of Banks
(ORGANIZATION OF BANKS ON BUSSES MAY RESTRICT BANDWIDTH)
8 Banks
16 Banks
4 Banks
2 Banks
2 DRAM Data Bus 1 DRAM Data Bus
Figure 3–8. Data Cycle Time Versus Increasing EDO DRAM Banks and Busses
The above graphs characterize the J Class memory system average cycle time (ACT) and bandwidth for
each of the supported configurations. The indicated data points show the effect of increasing numbers of
banks and busses on memory system ACT. The two, four, eight, and 16 memory bank configurations,
along with 1 and 2 DRAM Data busses, when applicable, are shown. The top horizontal axis shows the
absolute minimum cycle time possible for the combination of memory banks.
It should be pointed out that the above plotted numbers do not reflect the effect of queue size and
transaction time–variance on issue rate, which is a primary factor used in determining total system cycle
time. To understand a closer approximation to actual system throughput and cycle time, the queue size
and variance must be considered. A simple approximation can be derived from knowing the queue size
and assuming Poisson transaction arrivals. This approximates the “better” case behavior of the system.
Any significant work load variance is likely to degrade the issue rate beyond this point when it exceeds
the benefit of the queue.
We can estimate the issue rate by knowing the ACT (E[S]), the average retirement rate ( ), and the
average queue length (E[N]). The average issue rate ( ) can be derived assuming Poisson arrivals.