HP Visualize J200, Reference Manual

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Memory System Block Diagram
The J Class memory system is constructed from four major components: the Master Memory Controller,
Slave Memory Controllers, plug in memory modules (SIMMs), and data accumulate/MUX chips
(DRAM Data Path MUX). Figure 3–1 shows a block diagram of the J Class memory system.
The basic unit of memory is called a bank. Each bank of memory is 16 data bytes wide and can be accessed
independently from all other banks. A 32–byte cache line is read or written in two chunks using page
mode accesses to a bank; two pieces of data are transferred to/from a bank to make up a cache line.
Each multibank DRAM controller chip supports up to four independent memory banks. Since system
performance is highly dependent on the number of banks, the SIMMs are designed so that each SIMM
contains eight data bytes of two banks. Since a bank is 16 data bytes wide, the minimum memory
increment is two SIMMs, which yields two complete banks. The two banks on the two SIMMs have
independent address and control signals. 16 bits of ECC are included for each 16 bytes (128 bits) of data,
so a memory data bus carrying 16 bytes of data requires 144 bits total (128 data + 16 ECC = 144 total).
The 16–byte data bus (MD_H) that connects the Master Memory Controller chip to the DRAM Data Path
MUX chips operates at 60MHz, for a peak bandwidth of 960MB/sec. Memory banks are connected to the
DRAM Data Path MUX chips via 16–byte data buses (RDA_H, RDB_H). The RDA and RDB buses can
deliver two 16–byte pieces of data every four, five, or six 60MHz cycles, depending on whether the
transaction is a EDO read, a non–EDO read, or a write, respectively. These correspond to peak RDx_H
bandwidths of 480MB/s, 384MB/s, or 320MB/s, respectively. However, the RDx_H buses are
independent, so if memory accesses map to alternate buses, the peak bandwidth available from RDA_H
and RDB_H equals the peak bandwidth of MD_H. The actual bandwidth depends on the memory access
pattern, which in turn depends on the workload, the processors, and other factors.
The set of signals connecting the Master Memory Controller chip to multibank DRAM Controller and
DRAM Data Path MUX chips is collectively known as the MSI bus (Master Slave Interconnect).
A single cache line transfer requires two cycles of data on MD_H and RDx_H. Since data is transferred
over RDx_H at 1/2 the speed of MD_H, the DRAM Data Path MUX chips are responsible for
accumulating and distributing data between the MUX data bus (MD_H) and the RAM data buses
(RDx_H). Also note that to reduce the cost of the DRAM Data Path MUX chips, the design is bit sliced
across 4 identical chips. In other words, each DRAM Data Path MUX chip set consists of 4 identical
DRAM Data Path MUX chips.
J Class systems use one set of DRAM Data Path MUX chips as shown in the block diagram, and four
multibank DRAM controller chips. This allows for up to 1GB of memory (16Mb DRAMs).